From: Nathan Binkert <binkertn@umich.edu>
Date: Mon, 21 Nov 2005 05:02:39 +0000 (-0500)
Subject: BARs now of type MemorySize32
X-Git-Tag: m5_2.0_beta1~287
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4678ece8414230005e7a9e41e50e48c1bba66d7;p=gem5.git

BARs now of type MemorySize32

python/m5/config.py:
    Add MemorySize32 (a 32-bit value specified in bytes)

--HG--
extra : convert_revision : bfeee501f7ff1aa2567a3682da129a5770cb7bd2
---

diff --git a/python/m5/config.py b/python/m5/config.py
index 23292d2dc..a954012ea 100644
--- a/python/m5/config.py
+++ b/python/m5/config.py
@@ -972,6 +972,15 @@ class MemorySize(CheckedInt):
             self.value = toMemorySize(value)
         self._check()
 
+class MemorySize32(CheckedInt):
+    size = 32
+    unsigned = True
+    def __init__(self, value):
+        if isinstance(value, MemorySize):
+            self.value = value.value
+        else:
+            self.value = toMemorySize(value)
+        self._check()
 
 class Addr(CheckedInt):
     size = 64
@@ -1305,7 +1314,8 @@ __all__ = ['SimObject', 'ParamContext', 'Param', 'VectorParam',
            'Int32', 'UInt32', 'Int64', 'UInt64',
            'Counter', 'Addr', 'Tick', 'Percent',
            'TcpPort', 'UdpPort', 'EthernetAddr',
-           'MemorySize', 'Latency', 'Frequency', 'RootClock', 'Clock',
+           'MemorySize', 'MemorySize32',
+           'Latency', 'Frequency', 'RootClock', 'Clock',
            'NetworkBandwidth', 'MemoryBandwidth',
            'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory',
            'Null', 'NULL',
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py
index defdd10a3..4124d0b92 100644
--- a/python/m5/objects/Pci.py
+++ b/python/m5/objects/Pci.py
@@ -22,12 +22,12 @@ class PciConfigData(SimObject):
     BAR3 = Param.UInt32(0x00, "Base Address Register 3")
     BAR4 = Param.UInt32(0x00, "Base Address Register 4")
     BAR5 = Param.UInt32(0x00, "Base Address Register 5")
-    BAR0Size = Param.UInt32(0, "Base Address Register 0 Size")
-    BAR1Size = Param.UInt32(0, "Base Address Register 1 Size")
-    BAR2Size = Param.UInt32(0, "Base Address Register 2 Size")
-    BAR3Size = Param.UInt32(0, "Base Address Register 3 Size")
-    BAR4Size = Param.UInt32(0, "Base Address Register 4 Size")
-    BAR5Size = Param.UInt32(0, "Base Address Register 5 Size")
+    BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
+    BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
+    BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
+    BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
+    BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
+    BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
 
     CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
     SubsystemID = Param.UInt16(0x00, "Subsystem ID")