From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 13 May 2021 21:01:54 +0000 (+0100)
Subject: update comments in issuer.py regarding a 4th FSM
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4687172ead37c6e01fe90192d89c574e7bdc3b7;p=soc.git

update comments in issuer.py regarding a 4th FSM
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 477e81a4..667347f8 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1007,8 +1007,9 @@ class TestIssuerInternal(Elaboratable):
         # on VL==0
         is_svp64_mode = Signal()
 
-        # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
-        # these are the handshake signals between fetch and decode/execute
+        # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
+        # issue, decode/execute, now joined by "Predicate fetch/calculate".
+        # these are the handshake signals between each
 
         # fetch FSM can run as soon as the PC is valid
         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"