From: Gedare Bloom <gedare@rtems.org>
Date: Wed, 24 May 2017 22:35:50 +0000 (-0400)
Subject: arch-arm: fix ldm of pc interswitching branch
X-Git-Tag: v19.0.0.0~2685
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c473bdb8916528be4ff896c5e9378e6200f68939;p=gem5.git

arch-arm: fix ldm of pc interswitching branch

The LDM instruction that loads to the PC causes a branch to the
instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes.
The interswitch is broken prior to this commit, with LDM to the PC
ignoring the switch.

Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05
Reviewed-on: https://gem5-review.googlesource.com/3520
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index cc7366e2b..6a33d1b9f 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -58,7 +58,8 @@ let {{
     microLdr2UopCode = '''
                         uint64_t data = Mem_ud;
                         Dest = cSwap((uint32_t) data, ((CPSR)Cpsr).e);
-                        Dest2 = cSwap((uint32_t) (data >> 32), ((CPSR)Cpsr).e);
+                        IWDest2 = cSwap((uint32_t) (data >> 32),
+                                        ((CPSR)Cpsr).e);
                         '''
     microLdr2UopIop = InstObjParams('ldr2_uop', 'MicroLdr2Uop',
                                    'MicroMemPairOp',
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 5898075ab..2e2955a80 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -193,6 +193,7 @@ def operands {{
     'Dest2': intReg('dest2'),
     'XDest2': intRegX64('dest2'),
     'FDest2': floatReg('dest2'),
+    'IWDest2': intRegIWPC('dest2'),
     'Result': intReg('result'),
     'XResult': intRegX64('result'),
     'XBase': intRegX64('base', id = srtBase),