From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 9 May 2022 13:40:46 +0000 (+0100)
Subject: update comments on sv.svstep
X-Git-Tag: sv_maxu_works-initial~434
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4834fb62c0a910a5b3623a853744c26b4ce1858;p=openpower-isa.git

update comments on sv.svstep
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index dfe3ce18..11994cf8 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -209,9 +209,9 @@ class SVP64Asm:
             yield ".long 0x%x" % insn
             return
 
-        # this is a *32-bit-only* instruction. it updates SVSTATE.
-        # it is *not* a 64-bit-prefixed Vector instruction (no sv.svstep),
-        # it is a Vector *control* instruction.
+        # this is a 32-bit instruction. it updates SVSTATE.
+        # it *can* be SVP64-prefixed, to indicate that its registers
+        # are Vectorised.
         # note: EXT022 is the "sandbox" major opcode so it's fine to add
 
         # sigh have to do setvl here manually for now...