From: clairexen Date: Thu, 16 Jul 2020 16:28:24 +0000 (+0200) Subject: Merge pull request #2272 from whitequark/write-verilog-sv X-Git-Tag: working-ls180~376 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c49344b262b455bf03239a5bc7453f0706cc45d8;p=yosys.git Merge pull request #2272 from whitequark/write-verilog-sv verilog_backend: add `-sv` option, make `-o .sv` work --- c49344b262b455bf03239a5bc7453f0706cc45d8