From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 23 Aug 2020 19:49:13 +0000 (+0100)
Subject: bring "core stopped" signal out through DMI interface
X-Git-Tag: semi_working_ecp5~272^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c495f10fdbbc2bdaf0e304db5a709e0c585de9c2;p=soc.git

bring "core stopped" signal out through DMI interface
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index ad4fd0a9..cf516099 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -156,9 +156,9 @@ class TestIssuer(Elaboratable):
 
         # connect up debug signals
         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
-        comb += core.core_stopped_i.eq(dbg.core_stop_o)
         comb += dbg.terminate_i.eq(core.core_terminate_o)
         comb += dbg.state.pc.eq(pc)
+        #comb += dbg.state.pc.eq(cur_state.pc)
         comb += dbg.state.msr.eq(cur_state.msr)
 
         # temporaries
@@ -195,6 +195,9 @@ class TestIssuer(Elaboratable):
                     comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
 
                     m.next = "INSN_READ" # move to "wait for bus" phase
+                with m.Else():
+                    comb += core.core_stopped_i.eq(1)
+                    comb += dbg.core_stopped_i.eq(1)
 
             # dummy pause to find out why simulation is not keeping up
             with m.State("INSN_READ"):