From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 22:02:53 +0000 (-0700)
Subject: Another oops
X-Git-Tag: working-ls180~1039^2~220
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c497114e94286c06fe16a6ae32e2873578a861f4;p=yosys.git

Another oops
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index b03fff8ec..66fe7736b 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -101,7 +101,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 			SigSpec Q = st.ffM->getPort("\\Q");
 			P.replace(pm.sigmap(D), Q);
 			cell->setParam("\\MREG", State::S1);
-			if (st.ffP->type == "$dff")
+			if (st.ffM->type == "$dff")
 				cell->setPort("\\CEM", State::S1);
 			//else if (st.ffP->type == "$dffe")
 			//	cell->setPort("\\CEM", st.ffM->getPort("\\EN"));