From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 5 Sep 2017 04:49:56 +0000 (-0700)
Subject: Fixed typo in comment. Fixed bug where extract_counter would create up counters when... 
X-Git-Tag: yosys-0.8~320^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4a70a8cc32e3eefca678d2d0ed569078423f994;p=yosys.git

Fixed typo in comment. Fixed bug where extract_counter would create up counters when it meant to create down counters.
---

diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index 540b1593d..de374ab2b 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -424,12 +424,12 @@ void counter_worker(
 	cell->setPort("\\CLK", extract.clk);
 	cell->setPort("\\OUT", extract.outsig);
 
-	//Hook up hard-wired ports (for now CE and up/=down are not supported), default to no parallel output
+	//Hook up hard-wired ports (for now CE and up/down are not supported), default to no parallel output
 	cell->setParam("\\HAS_POUT", RTLIL::Const(0));
 	cell->setParam("\\HAS_CE", RTLIL::Const(0));
 	cell->setParam("\\DIRECTION", RTLIL::Const("DOWN"));
 	cell->setPort("\\CE", RTLIL::Const(1));
-	cell->setPort("\\UP", RTLIL::Const(1));
+	cell->setPort("\\UP", RTLIL::Const(0));
 
 	//Hook up any parallel outputs
 	for(auto load : extract.pouts)