From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 13:50:39 +0000 (+0100)
Subject: output ilang for ALU to unique file
X-Git-Tag: div_pipeline~1042
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4bdff672d08114bcdea3aa37a25bc9c34264b1c;p=soc.git

output ilang for ALU to unique file
---

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 9a9e5571..935e272f 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -166,7 +166,7 @@ class ALUTestCase(FHDLTestCase):
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = ALUBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
-        with open("pipeline.il", "w") as f:
+        with open("alu_pipeline.il", "w") as f:
             f.write(vl)