From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 14 Jul 2020 10:42:29 +0000 (+0100)
Subject: disable cxxsim test
X-Git-Tag: div_pipeline~48
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4beb6416975c7c9af38afe28bc85bd250ec148c;p=soc.git

disable cxxsim test
---

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index bbd496ba..fdb2089a 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Delay, Settle
-cxxsim = True
+cxxsim = False
 if cxxsim:
     from nmigen.sim.cxxsim import Simulator
 else: