From: lkcl <lkcl@web>
Date: Sun, 14 Nov 2021 18:23:35 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3387
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4ca0470c5f25c94a3f6e67fd61d9142870186ab;p=libreriscv.git

---

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 45b1a8d82..2f5d5b58a 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -28,11 +28,11 @@ at very low frequencies (5 khz is perfectly acceptable)
 so there is very little risk of clock skew during that testing.
 
 Additionally, an SoC is designed to be low cost, to use low cost
-packaging. ASICs are typically 32 to 128 pins QFP
-only in the Embedded
+packaging. ASICs are typically only 32 to 128 pins QFP
+in the Embedded
 Controller range, and between 300 to 650 FBGA in the Tablet /
 Smartphone range, absolute maximum of 19 mm on a side.
-1,000 pin packages common to Intel desktop processors are
+2 to 3 in square 1,000 pin packages common to Intel desktop processors are
 absolutely out of the question.
 
 (*With each pin wire bond smashing