From: Kevin Lim Date: Fri, 11 Feb 2005 22:54:33 +0000 (-0500) Subject: Fix up #defines to use full path; fix up code for g++ 3.4 X-Git-Tag: m5_1.0_tutorial~76^2~6 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4d0ebd25cc5f0657b99543ff2df30d1a86f3ad5;p=gem5.git Fix up #defines to use full path; fix up code for g++ 3.4 SConscript: Remove efence option from automatically being used. --HG-- extra : convert_revision : 466bb8077aa341db0b409720e2a73535b1fa6b69 --- diff --git a/SConscript b/SConscript index 6d7ed172f..54f16fce6 100644 --- a/SConscript +++ b/SConscript @@ -432,7 +432,7 @@ env.Append(CPPPATH='.') # Debug binary debug = env.Copy(OBJSUFFIX='.do') -debug.Append(CCFLAGS=Split('-g -gstabs+ -O0 -lefence')) +debug.Append(CCFLAGS=Split('-g -gstabs+ -O0')) debug.Append(CPPDEFINES='DEBUG') debug.Program(target = 'm5.debug', source = make_objs(sources, debug)) diff --git a/cpu/beta_cpu/alpha_dyn_inst.hh b/cpu/beta_cpu/alpha_dyn_inst.hh index c964762db..584e027d7 100644 --- a/cpu/beta_cpu/alpha_dyn_inst.hh +++ b/cpu/beta_cpu/alpha_dyn_inst.hh @@ -1,7 +1,7 @@ //Todo: -#ifndef __ALPHA_DYN_INST_HH__ -#define __ALPHA_DYN_INST_HH__ +#ifndef __CPU_BETA_CPU_ALPHA_DYN_INST_HH__ +#define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__ #include "cpu/base_dyn_inst.hh" #include "cpu/beta_cpu/alpha_full_cpu.hh" @@ -76,5 +76,5 @@ class AlphaDynInst : public BaseDynInst }; -#endif // __ALPHA_DYN_INST_HH__ +#endif // __CPU_BETA_CPU_ALPHA_DYN_INST_HH__ diff --git a/cpu/beta_cpu/alpha_full_cpu.hh b/cpu/beta_cpu/alpha_full_cpu.hh index e01eba3bf..92eebc82a 100644 --- a/cpu/beta_cpu/alpha_full_cpu.hh +++ b/cpu/beta_cpu/alpha_full_cpu.hh @@ -3,16 +3,12 @@ // Read and write are horribly hacked up between not being sure where to // copy their code from, and Ron's memory changes. -#ifndef __ALPHA_FULL_CPU_HH__ -#define __ALPHA_FULL_CPU_HH__ +#ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__ +#define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__ // To include: comm, full cpu, ITB/DTB if full sys, -//#include "cpu/beta_cpu/comm.hh" -//#include "cpu/beta_cpu/alpha_impl.hh" #include "cpu/beta_cpu/full_cpu.hh" -using namespace std; - template class AlphaFullCPU : public FullBetaCPU { @@ -250,4 +246,4 @@ class AlphaFullCPU : public FullBetaCPU }; -#endif // __ALPHA_FULL_CPU_HH__ +#endif // __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__ diff --git a/cpu/beta_cpu/alpha_impl.hh b/cpu/beta_cpu/alpha_impl.hh index fc86dacd7..81a1aba9b 100644 --- a/cpu/beta_cpu/alpha_impl.hh +++ b/cpu/beta_cpu/alpha_impl.hh @@ -1,5 +1,5 @@ -#ifndef __ALPHA_IMPL_HH__ -#define __ALPHA_IMPL_HH__ +#ifndef __CPU_BETA_CPU_ALPHA_IMPL_HH__ +#define __CPU_BETA_CPU_ALPHA_IMPL_HH__ #include "arch/alpha/isa_traits.hh" @@ -51,4 +51,4 @@ struct AlphaSimpleImpl }; }; -#endif // __ALPHA_IMPL_HH__ +#endif // __CPU_BETA_CPU_ALPHA_IMPL_HH__ diff --git a/cpu/beta_cpu/comm.hh b/cpu/beta_cpu/comm.hh index e327a83b9..c0afe3d1b 100644 --- a/cpu/beta_cpu/comm.hh +++ b/cpu/beta_cpu/comm.hh @@ -1,13 +1,11 @@ -#ifndef __COMM_HH__ -#define __COMM_HH__ +#ifndef __CPU_BETA_CPU_COMM_HH__ +#define __CPU_BETA_CPU_COMM_HH__ #include #include #include "arch/alpha/isa_traits.hh" #include "cpu/inst_seq.hh" -using namespace std; - // Find better place to put this typedef. // The impl might be the best place for this. typedef short int PhysRegIndex; @@ -18,7 +16,7 @@ struct SimpleFetchSimpleDecode { int size; - DynInstPtr insts[Impl::MaxWidth + 1]; + DynInstPtr insts[Impl::MaxWidth]; }; template @@ -27,7 +25,7 @@ struct SimpleDecodeSimpleRename { int size; - DynInstPtr insts[Impl::MaxWidth + 1]; + DynInstPtr insts[Impl::MaxWidth]; }; template @@ -36,7 +34,7 @@ struct SimpleRenameSimpleIEW { int size; - DynInstPtr insts[Impl::MaxWidth + 1]; + DynInstPtr insts[Impl::MaxWidth]; }; template @@ -45,7 +43,7 @@ struct SimpleIEWSimpleCommit { int size; - DynInstPtr insts[Impl::MaxWidth + 1]; + DynInstPtr insts[Impl::MaxWidth]; bool squash; bool branchMispredict; @@ -62,7 +60,7 @@ struct IssueStruct { int size; - DynInstPtr insts[Impl::MaxWidth + 1]; + DynInstPtr insts[Impl::MaxWidth]; }; struct TimeBufStruct { @@ -142,4 +140,4 @@ struct TimeBufStruct { commitComm commitInfo; }; -#endif //__COMM_HH__ +#endif //__CPU_BETA_CPU_COMM_HH__ diff --git a/cpu/beta_cpu/commit.cc b/cpu/beta_cpu/commit.cc index 2efb38976..9e8fa2781 100644 --- a/cpu/beta_cpu/commit.cc +++ b/cpu/beta_cpu/commit.cc @@ -1,6 +1,6 @@ #include "cpu/beta_cpu/alpha_dyn_inst.hh" -#include "cpu/beta_cpu/commit_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/commit_impl.hh" -template SimpleCommit; +template class SimpleCommit; diff --git a/cpu/beta_cpu/commit.hh b/cpu/beta_cpu/commit.hh index f1a185143..731307bf7 100644 --- a/cpu/beta_cpu/commit.hh +++ b/cpu/beta_cpu/commit.hh @@ -12,14 +12,11 @@ // Probably not a big deal if the IPR stuff isn't cycle accurate. Can just // have the original function handle writing to the IPR register. -#ifndef __SIMPLE_COMMIT_HH__ -#define __SIMPLE_COMMIT_HH__ +#ifndef __CPU_BETA_CPU_SIMPLE_COMMIT_HH__ +#define __CPU_BETA_CPU_SIMPLE_COMMIT_HH__ -//#include "arch/alpha/isa_traits.hh" +#include "base/statistics.hh" #include "base/timebuf.hh" -//#include "cpu/beta_cpu/comm.hh" -//#include "cpu/beta_cpu/rename_map.hh" -//#include "cpu/beta_cpu/rob.hh" #include "mem/memory_interface.hh" template @@ -157,4 +154,4 @@ class SimpleCommit Stats::Distribution<> n_committed_dist; }; -#endif // __SIMPLE_COMMIT_HH__ +#endif // __CPU_BETA_CPU_SIMPLE_COMMIT_HH__ diff --git a/cpu/beta_cpu/cpu_policy.hh b/cpu/beta_cpu/cpu_policy.hh index 1479eb191..6606aba29 100644 --- a/cpu/beta_cpu/cpu_policy.hh +++ b/cpu/beta_cpu/cpu_policy.hh @@ -1,5 +1,5 @@ -#ifndef __CPU_POLICY_HH__ -#define __CPU_POLICY_HH__ +#ifndef __CPU_BETA_CPU_CPU_POLICY_HH__ +#define __CPU_BETA_CPU_CPU_POLICY_HH__ #include "cpu/beta_cpu/bpred_unit.hh" #include "cpu/beta_cpu/inst_queue.hh" @@ -57,4 +57,4 @@ struct SimpleCPUPolicy }; -#endif //__CPU_POLICY_HH__ +#endif //__CPU_BETA_CPU_CPU_POLICY_HH__ diff --git a/cpu/beta_cpu/decode.cc b/cpu/beta_cpu/decode.cc index ffabcf18a..177293bca 100644 --- a/cpu/beta_cpu/decode.cc +++ b/cpu/beta_cpu/decode.cc @@ -1,6 +1,6 @@ #include "cpu/beta_cpu/alpha_dyn_inst.hh" -#include "cpu/beta_cpu/decode_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/decode_impl.hh" -template SimpleDecode; +template class SimpleDecode; diff --git a/cpu/beta_cpu/decode.hh b/cpu/beta_cpu/decode.hh index 64e87290e..dd18cf176 100644 --- a/cpu/beta_cpu/decode.hh +++ b/cpu/beta_cpu/decode.hh @@ -5,11 +5,12 @@ // Fix up squashing too, as it's too // dependent upon the iew stage continually telling it to squash. -#ifndef __SIMPLE_DECODE_HH__ -#define __SIMPLE_DECODE_HH__ +#ifndef __CPU_BETA_CPU_SIMPLE_DECODE_HH__ +#define __CPU_BETA_CPU_SIMPLE_DECODE_HH__ #include +#include "base/statistics.hh" #include "base/timebuf.hh" template @@ -141,4 +142,4 @@ class SimpleDecode Stats::Scalar<> decodeSquashedInsts; }; -#endif // __SIMPLE_DECODE_HH__ +#endif // __CPU_BETA_CPU_SIMPLE_DECODE_HH__ diff --git a/cpu/beta_cpu/decode_impl.hh b/cpu/beta_cpu/decode_impl.hh index dd51f564d..9d88f94ac 100644 --- a/cpu/beta_cpu/decode_impl.hh +++ b/cpu/beta_cpu/decode_impl.hh @@ -1,6 +1,3 @@ -#ifndef __SIMPLE_DECODE_CC__ -#define __SIMPLE_DECODE_CC__ - #include "cpu/beta_cpu/decode.hh" template @@ -392,5 +389,3 @@ SimpleDecode::decode() numInst = 0; } - -#endif // __SIMPLE_DECODE_CC__ diff --git a/cpu/beta_cpu/fetch.cc b/cpu/beta_cpu/fetch.cc index 4d08754b6..877262750 100644 --- a/cpu/beta_cpu/fetch.cc +++ b/cpu/beta_cpu/fetch.cc @@ -1,7 +1,6 @@ #include "cpu/beta_cpu/alpha_dyn_inst.hh" -#include "cpu/beta_cpu/alpha_full_cpu.hh" -#include "cpu/beta_cpu/fetch_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/fetch_impl.hh" -template SimpleFetch; +template class SimpleFetch; diff --git a/cpu/beta_cpu/fetch.hh b/cpu/beta_cpu/fetch.hh index 4cfc2f167..7a3893708 100644 --- a/cpu/beta_cpu/fetch.hh +++ b/cpu/beta_cpu/fetch.hh @@ -4,17 +4,17 @@ // Figure out where to advance time buffer. Add a way to get a // stage's current status. -#ifndef __SIMPLE_FETCH_HH__ -#define __SIMPLE_FETCH_HH__ +#ifndef __CPU_BETA_CPU_SIMPLE_FETCH_HH__ +#define __CPU_BETA_CPU_SIMPLE_FETCH_HH__ //Will want to include: time buffer, structs, MemInterface, Event, //whatever class bzero uses, MemReqPtr +#include "base/statistics.hh" #include "base/timebuf.hh" -#include "sim/eventq.hh" #include "cpu/pc_event.hh" #include "mem/mem_interface.hh" -#include "base/statistics.hh" +#include "sim/eventq.hh" /** * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch @@ -207,4 +207,4 @@ class SimpleFetch Stats::Distribution<> fetch_nisn_dist; }; -#endif //__SIMPLE_FETCH_HH__ +#endif //__CPU_BETA_CPU_SIMPLE_FETCH_HH__ diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/beta_cpu/full_cpu.hh index bde7e5bbf..19eb972d9 100644 --- a/cpu/beta_cpu/full_cpu.hh +++ b/cpu/beta_cpu/full_cpu.hh @@ -20,8 +20,6 @@ #include "cpu/beta_cpu/cpu_policy.hh" #include "sim/process.hh" -using namespace std; - class FunctionalMemory; class Process; diff --git a/cpu/beta_cpu/iew.cc b/cpu/beta_cpu/iew.cc index 8abb2f196..a90d64434 100644 --- a/cpu/beta_cpu/iew.cc +++ b/cpu/beta_cpu/iew.cc @@ -1,8 +1,7 @@ #include "cpu/beta_cpu/alpha_dyn_inst.hh" -#include "cpu/beta_cpu/inst_queue.hh" -#include "cpu/beta_cpu/iew_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/iew_impl.hh" +#include "cpu/beta_cpu/inst_queue.hh" -template SimpleIEW; +template class SimpleIEW; diff --git a/cpu/beta_cpu/iew.hh b/cpu/beta_cpu/iew.hh index 90bd39e7f..e3e7c6db5 100644 --- a/cpu/beta_cpu/iew.hh +++ b/cpu/beta_cpu/iew.hh @@ -2,14 +2,14 @@ //Need to handle delaying writes to the writeback bus if it's full at the //given time. Load store queue. -#ifndef __SIMPLE_IEW_HH__ -#define __SIMPLE_IEW_HH__ +#ifndef __CPU_BETA_CPU_SIMPLE_IEW_HH__ +#define __CPU_BETA_CPU_SIMPLE_IEW_HH__ #include +#include "base/statistics.hh" #include "base/timebuf.hh" #include "cpu/beta_cpu/comm.hh" -#include "base/statistics.hh" //Can IEW even stall? Space should be available/allocated already...maybe //if there's not enough write ports on the ROB or waiting for CDB @@ -187,4 +187,4 @@ class SimpleIEW Stats::Scalar<> predictedTakenIncorrect; }; -#endif +#endif // __CPU_BETA_CPU_IEW_HH__ diff --git a/cpu/beta_cpu/regfile.hh b/cpu/beta_cpu/regfile.hh index f6fb917ba..a81ed63bc 100644 --- a/cpu/beta_cpu/regfile.hh +++ b/cpu/beta_cpu/regfile.hh @@ -3,8 +3,6 @@ // @todo: Destructor -using namespace std; - #include "arch/alpha/isa_traits.hh" #include "cpu/beta_cpu/comm.hh" diff --git a/cpu/beta_cpu/rename.cc b/cpu/beta_cpu/rename.cc index bcce7ef49..1feec4342 100644 --- a/cpu/beta_cpu/rename.cc +++ b/cpu/beta_cpu/rename.cc @@ -1,6 +1,6 @@ #include "cpu/beta_cpu/alpha_dyn_inst.hh" -#include "cpu/beta_cpu/rename_impl.hh" #include "cpu/beta_cpu/alpha_impl.hh" +#include "cpu/beta_cpu/rename_impl.hh" -template SimpleRename; +template class SimpleRename; diff --git a/cpu/beta_cpu/rename.hh b/cpu/beta_cpu/rename.hh index 3e6b873ae..3e9899718 100644 --- a/cpu/beta_cpu/rename.hh +++ b/cpu/beta_cpu/rename.hh @@ -3,11 +3,12 @@ // May want to have different statuses to differentiate the different stall // conditions. -#ifndef __SIMPLE_RENAME_HH__ -#define __SIMPLE_RENAME_HH__ +#ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__ +#define __CPU_BETA_CPU_SIMPLE_RENAME_HH__ #include +#include "base/statistics.hh" #include "base/timebuf.hh" // Will need rename maps for both the int reg file and fp reg file. @@ -202,4 +203,4 @@ class SimpleRename Stats::Scalar<> renameValidUndoneMaps; }; -#endif // __SIMPLE_RENAME_HH__ +#endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__ diff --git a/cpu/beta_cpu/rename_map.hh b/cpu/beta_cpu/rename_map.hh index e68fa05a8..44a7eefb1 100644 --- a/cpu/beta_cpu/rename_map.hh +++ b/cpu/beta_cpu/rename_map.hh @@ -2,17 +2,15 @@ // Have it so that there's a more meaningful name given to the variable // that marks the beginning of the FP registers. -#ifndef __RENAME_MAP_HH__ -#define __RENAME_MAP_HH__ +#ifndef __CPU_BETA_CPU_RENAME_MAP_HH__ +#define __CPU_BETA_CPU_RENAME_MAP_HH__ #include -#include #include +#include #include "cpu/beta_cpu/free_list.hh" -using namespace std; - class SimpleRenameMap { public: @@ -21,7 +19,7 @@ class SimpleRenameMap * previous mapping of a logical register to a physical register. * Used to roll back the rename map to a previous state. */ - typedef pair UnmapInfo; + typedef std::pair UnmapInfo; /** * Pair of a physical register and a physical register. Used to @@ -29,7 +27,7 @@ class SimpleRenameMap * renamed to, and the previous physical register that the same * logical register was previously mapped to. */ - typedef pair RenameInfo; + typedef std::pair RenameInfo; public: //Constructor @@ -128,17 +126,17 @@ class SimpleRenameMap /** Scoreboard of physical integer registers, saying whether or not they * are ready. */ - vector intScoreboard; + std::vector intScoreboard; /** Scoreboard of physical floating registers, saying whether or not they * are ready. */ - vector floatScoreboard; + std::vector floatScoreboard; /** Scoreboard of miscellaneous registers, saying whether or not they * are ready. */ - vector miscScoreboard; + std::vector miscScoreboard; }; -#endif //__RENAME_MAP_HH__ +#endif //__CPU_BETA_CPU_RENAME_MAP_HH__ diff --git a/cpu/beta_cpu/rob.hh b/cpu/beta_cpu/rob.hh index c921c0619..da6b5232a 100644 --- a/cpu/beta_cpu/rob.hh +++ b/cpu/beta_cpu/rob.hh @@ -4,15 +4,13 @@ // all instructions after the instruction, and all instructions after *and* // including that instruction. -#ifndef __ROB_HH__ -#define __ROB_HH__ +#ifndef __CPU_BETA_CPU_ROB_HH__ +#define __CPU_BETA_CPU_ROB_HH__ -#include -#include +#include +#include -#include "arch/alpha/isa_traits.hh" - -using namespace std; +//#include "arch/alpha/isa_traits.hh" /** * ROB class. Uses the instruction list that exists within the CPU to @@ -28,7 +26,7 @@ class ROB typedef typename Impl::FullCPU FullCPU; typedef typename Impl::DynInstPtr DynInstPtr; - typedef pair UnmapInfo_t; + typedef std::pair UnmapInfo_t; typedef typename list::iterator InstIt_t; public: @@ -135,4 +133,4 @@ class ROB bool doneSquashing; }; -#endif //__ROB_HH__ +#endif //__CPU_BETA_CPU_ROB_HH__