From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 16 Dec 2019 18:41:13 +0000 (-0800)
Subject: Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
X-Git-Tag: working-ls180~921^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4d37813cb112d7f3717049d7cf4e6e6b0456fbb;p=yosys.git

Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
---

diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt
index ae629bce8..29f6b05cc 100644
--- a/techlibs/xilinx/lutrams.txt
+++ b/techlibs/xilinx/lutrams.txt
@@ -78,7 +78,7 @@ bram $__XILINX_RAM64X3SDP
   clkpol 0 2
 endbram
 
-bram $__XILINX_RAM32M
+bram $__XILINX_RAM32X2Q
   init 1
   abits 5
   dbits 2
@@ -91,7 +91,7 @@ bram $__XILINX_RAM32M
   clkpol 0 2
 endbram
 
-bram $__XILINX_RAM64M
+bram $__XILINX_RAM64X1Q
   init 1
   abits 6
   dbits 1
@@ -151,7 +151,7 @@ match $__XILINX_RAM64X3SDP
   or_next_if_better
 endmatch
 
-match $__XILINX_RAM32M
+match $__XILINX_RAM32X2Q
   min bits 5
   min rports 3
   min wports 1
@@ -159,7 +159,7 @@ match $__XILINX_RAM32M
   or_next_if_better
 endmatch
 
-match $__XILINX_RAM64M
+match $__XILINX_RAM64X1Q
   min bits 5
   min rports 3
   min wports 1
diff --git a/techlibs/xilinx/lutrams_map.v b/techlibs/xilinx/lutrams_map.v
index d01508de5..884f709ab 100644
--- a/techlibs/xilinx/lutrams_map.v
+++ b/techlibs/xilinx/lutrams_map.v
@@ -200,7 +200,7 @@ module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	);
 endmodule
 
-module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAM32X2Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
 	parameter [63:0] INIT = 64'bx;
 	parameter CLKPOL2 = 1;
 	input CLK1;
@@ -236,7 +236,7 @@ module \$__XILINX_RAM32M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA,
 	);
 endmodule
 
-module \$__XILINX_RAM64M (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
 	parameter [63:0] INIT = 64'bx;
 	parameter CLKPOL2 = 1;
 	input CLK1;