From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 25 Jun 2019 15:29:55 +0000 (-0700)
Subject: Move only one consumer check outside of while loop
X-Git-Tag: yosys-0.9~46^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4e4902098153a4ab90d383ffc00987fc06ff072;p=yosys.git

Move only one consumer check outside of while loop
---

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index d37cac28e..91ae38fa3 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -189,16 +189,15 @@ struct MemoryDffWorker
 				bool enable_invert = mux_cells_a.count(sig_data) != 0;
 				Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
 				check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
-
 				sig_data = sigmap(mux->getPort("\\Y"));
-				for (auto bit : sig_data)
-					if (sigbit_users_count[bit] > 1) {
-						goto skip_ff_after_read_merging;
-					}
-
 				en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
 			} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
 
+                        for (auto bit : sig_data)
+                                if (sigbit_users_count[bit] > 1) {
+                                        goto skip_ff_after_read_merging;
+                                }
+
 			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
 			{
 				disconnect_dff(sig_data);