From: David Hashe <david.hashe@amd.com>
Date: Mon, 20 Jul 2015 14:15:18 +0000 (-0500)
Subject: ruby: expose access permission to replacement policies
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c4ffd4989c35a4afea1097fec97ac5bcd52974b3;p=gem5.git

ruby: expose access permission to replacement policies

This patch adds support that allows the replacement policy to identify each
cache block's access permission.  This information can be useful when making
replacement decisions.
---

diff --git a/src/mem/ruby/structures/AbstractReplacementPolicy.hh b/src/mem/ruby/structures/AbstractReplacementPolicy.hh
index d007c98c8..03ef0d2fd 100644
--- a/src/mem/ruby/structures/AbstractReplacementPolicy.hh
+++ b/src/mem/ruby/structures/AbstractReplacementPolicy.hh
@@ -34,6 +34,8 @@
 #include "params/ReplacementPolicy.hh"
 #include "sim/sim_object.hh"
 
+class CacheMemory;
+
 class AbstractReplacementPolicy : public SimObject
 {
   public:
@@ -52,6 +54,9 @@ class AbstractReplacementPolicy : public SimObject
 
     virtual bool useOccupancy() const { return false; }
 
+    void setCache(CacheMemory * pCache) {m_cache = pCache;}
+    CacheMemory * m_cache;
+
   protected:
     unsigned m_num_sets;       /** total number of sets */
     unsigned m_assoc;          /** set associativity */
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index d08724cff..e444ae09c 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -63,6 +63,7 @@ CacheMemory::CacheMemory(const Params *p)
     m_latency = p->latency;
     m_cache_assoc = p->assoc;
     m_replacementPolicy_ptr = p->replacement_policy;
+    m_replacementPolicy_ptr->setCache(this);
     m_start_index_bit = p->start_index_bit;
     m_is_instruction_only_cache = p->is_icache;
     m_resource_stalls = p->resourceStalls;
@@ -592,3 +593,15 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr)
         return true;
     }
 }
+
+bool
+CacheMemory::isBlockInvalid(int64 cache_set, int64 loc)
+{
+  return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
+}
+
+bool
+CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc)
+{
+  return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
+}
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index af5e680d8..57f2885b6 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -100,6 +100,8 @@ class CacheMemory : public SimObject
     Cycles getTagLatency() const { return tagArray.getLatency(); }
     Cycles getDataLatency() const { return dataArray.getLatency(); }
 
+    bool isBlockInvalid(int64 cache_set, int64 loc);
+    bool isBlockNotBusy(int64 cache_set, int64 loc);
 
     // Hook for checkpointing the contents of the cache
     void recordCacheContents(int cntrl, CacheRecorder* tr) const;