From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 18 Jun 2020 22:38:14 +0000 (+0200)
Subject: Add unit tests for delayed_enter
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c500b273324ec1af9b60270ec6b7ef0bdd0a4655;p=gram.git

Add unit tests for delayed_enter
---

diff --git a/gram/compat.py b/gram/compat.py
index 2485652..5bda031 100644
--- a/gram/compat.py
+++ b/gram/compat.py
@@ -29,37 +29,46 @@ def delayed_enter(m, src, dst, delay):
 
 class DelayedEnterTestCase(unittest.TestCase):
     def test_sequence(self):
-        m = Module()
-
-        before = Signal()
-        end = Signal()
-
-        with m.FSM():
-            with m.State("Before-Delayed-Enter"):
-                m.d.comb += before.eq(1)
-                m.next = "Delayed-Enter"
-
-            delayed_enter(m, "Delayed-Enter", "End-Delayed-Enter", 10)
-
-            with m.State("End-Delayed-Enter"):
-                m.d.comb += end.eq(1)
-
-        def process():
-            while (yield before):
-                yield
-
-            delay = 0
-            while not (yield end):
-                yield
-                delay += 1
-
-            self.assertEqual(delay, 10)
-
-        sim = Simulator(m)
-        with sim.write_vcd("test_compat.vcd"):
-            sim.add_clock(1e-6)
-            sim.add_sync_process(process)
-            sim.run()
+        def sequence(expected_delay):
+            m = Module()
+
+            before = Signal()
+            end = Signal()
+
+            with m.FSM():
+                with m.State("Before-Delayed-Enter"):
+                    m.d.comb += before.eq(1)
+                    m.next = "Delayed-Enter"
+
+                delayed_enter(m, "Delayed-Enter", "End-Delayed-Enter", expected_delay)
+
+                with m.State("End-Delayed-Enter"):
+                    m.d.comb += end.eq(1)
+
+            def process():
+                while (yield before):
+                    yield
+
+                delay = 0
+                while not (yield end):
+                    yield
+                    delay += 1
+
+                self.assertEqual(delay, expected_delay)
+
+            sim = Simulator(m)
+            with sim.write_vcd("test_compat.vcd"):
+                sim.add_clock(1e-6)
+                sim.add_sync_process(process)
+                sim.run()
+
+        with self.assertRaises(AssertionError):
+            sequence(0)
+        sequence(1)
+        sequence(2)
+        sequence(10)
+        sequence(100)
+        sequence(1000)
 
 class RoundRobin(Elaboratable):
     """A round-robin scheduler. (HarryHo90sHK)