From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Jul 2019 22:54:27 +0000 (-0700)
Subject: Signedness
X-Git-Tag: working-ls180~1039^2~354
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c501aa5ee84c14f5b6aebe3052dabb1c314eb9e0;p=yosys.git

Signedness
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1262fc8c1..33b2a8f62 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -386,15 +386,15 @@ module DSP48E1 (
     output [3:0] CARRYOUT,
     output MULTSIGNOUT,
     output OVERFLOW,
-    output reg [47:0] P,
+    output reg signed [47:0] P,
     output PATTERNBDETECT,
     output PATTERNDETECT,
     output [47:0] PCOUT,
     output UNDERFLOW,
-    input [29:0] A,
+    input signed [29:0] A,
     input [29:0] ACIN,
     input [3:0] ALUMODE,
-    input [17:0] B,
+    input signed [17:0] B,
     input [17:0] BCIN,
     input [47:0] C,
     input CARRYCASCIN,
@@ -494,9 +494,9 @@ module DSP48E1 (
 `endif
     end
 
-    reg [29:0] Ar;
-    reg [17:0] Br;
-    reg [47:0] Pr;
+    reg signed [29:0] Ar;
+    reg signed [17:0] Br;
+    reg signed [47:0] Pr;
     generate
         if (AREG == 1) begin always @(posedge CLK) if (CEA2) Ar <= A; end
         else           always @* Ar <= A;
@@ -516,7 +516,7 @@ module DSP48E1 (
         if (PCIN != 48'b0)          $fatal(1, "Unsupported PCIN value");
         if (CARRYIN != 1'b0)        $fatal(1, "Unsupported CARRYIN value");
 `endif
-        Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
+        Pr[42:0] <= $signed(Ar[24:0]) * Br;
     end
 
     generate
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v
index da1d6f3a9..28e456898 100644
--- a/techlibs/xilinx/dsp_map.v
+++ b/techlibs/xilinx/dsp_map.v
@@ -20,7 +20,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
 		.PREG(0)
 	) _TECHMAP_REPLACE_ (
 		//Data path
-		.A({5'b0, A}),
+		.A({{5{A[24]}}, A}),
 		.B(B),
 		.C(48'b0),
 		.D(24'b0),