From: Matt Turner Date: Tue, 24 Jun 2014 22:53:19 +0000 (-0700) Subject: i965: Use typed foreach_in_list instead of foreach_list. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5030ac0ac15d3c91c4352789f94281da9a9dcad;p=mesa.git i965: Use typed foreach_in_list instead of foreach_list. Acked-by: Ian Romanick --- diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp b/src/mesa/drivers/dri/i965/brw_cfg.cpp index 9d6eeb37523..07111f5ac42 100644 --- a/src/mesa/drivers/dri/i965/brw_cfg.cpp +++ b/src/mesa/drivers/dri/i965/brw_cfg.cpp @@ -107,9 +107,7 @@ cfg_t::cfg_t(exec_list *instructions) entry->start = (backend_instruction *) instructions->get_head(); - foreach_list(node, instructions) { - backend_instruction *inst = (backend_instruction *)node; - + foreach_in_list(backend_instruction, inst, instructions) { cur->end = inst; /* set_next_block wants the post-incremented ip */ diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 263127f2de1..4be9161659d 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1477,9 +1477,7 @@ fs_visitor::assign_curb_setup() prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8; /* Map the offsets in the UNIFORM file to fixed HW regs. */ - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == UNIFORM) { int uniform_nr = inst->src[i].reg + inst->src[i].reg_offset; @@ -1601,9 +1599,7 @@ fs_visitor::assign_urb_setup() /* Offset all the urb_setup[] index by the actual position of the * setup regs, now that the location of the constants has been chosen. */ - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { if (inst->opcode == FS_OPCODE_LINTERP) { assert(inst->src[2].file == HW_REG); inst->src[2].fixed_hw_reg.nr += urb_start; @@ -1664,9 +1660,7 @@ fs_visitor::split_virtual_grfs() false; } - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { /* If there's a SEND message that requires contiguous destination * registers, no splitting is allowed. */ @@ -1701,9 +1695,7 @@ fs_visitor::split_virtual_grfs() } } - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { if (inst->dst.file == GRF && split_grf[inst->dst.reg] && inst->dst.reg_offset != 0) { @@ -1743,9 +1735,7 @@ fs_visitor::compact_virtual_grfs() int remap_table[this->virtual_grf_count]; memset(remap_table, -1, sizeof(remap_table)); - foreach_list(node, &this->instructions) { - const fs_inst *inst = (const fs_inst *) node; - + foreach_in_list(const fs_inst, inst, &instructions) { if (inst->dst.file == GRF) remap_table[inst->dst.reg] = 0; @@ -1769,9 +1759,7 @@ fs_visitor::compact_virtual_grfs() this->virtual_grf_count = new_index; /* Patch all the instructions to use the newly renumbered registers */ - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *) node; - + foreach_in_list(fs_inst, inst, &instructions) { if (inst->dst.file == GRF) inst->dst.reg = remap_table[inst->dst.reg]; @@ -1862,9 +1850,7 @@ fs_visitor::assign_constant_locations() is_live[i] = false; } - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *) node; - + foreach_in_list(fs_inst, inst, &instructions) { for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -1933,9 +1919,7 @@ fs_visitor::assign_constant_locations() void fs_visitor::demote_pull_constants() { - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -1983,9 +1967,7 @@ fs_visitor::opt_algebraic() { bool progress = false; - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { switch (inst->opcode) { case BRW_OPCODE_MUL: if (inst->src[1].file != IMM) @@ -2556,9 +2538,7 @@ fs_visitor::insert_gen4_send_dependency_workarounds() void fs_visitor::lower_uniform_pull_constant_loads() { - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD) continue; @@ -2656,8 +2636,7 @@ fs_visitor::dump_instructions(const char *name) } int ip = 0, max_pressure = 0; - foreach_list(node, &this->instructions) { - backend_instruction *inst = (backend_instruction *)node; + foreach_in_list(backend_instruction, inst, &instructions) { max_pressure = MAX2(max_pressure, regs_live_at_ip[ip]); fprintf(file, "{%3d} %4d: ", regs_live_at_ip[ip], ip); dump_instruction(inst, file); @@ -2980,7 +2959,7 @@ fs_visitor::calculate_register_pressure() calculate_live_intervals(); int num_instructions = 0; - foreach_list(node, &this->instructions) { + foreach_in_list(fs_inst, inst, &instructions) { ++num_instructions; } @@ -3062,8 +3041,7 @@ fs_visitor::run() * functions called "main"). */ if (shader) { - foreach_list(node, &*shader->base.ir) { - ir_instruction *ir = (ir_instruction *)node; + foreach_in_list(ir_instruction, ir, shader->base.ir) { base_ir = ir; this->result = reg_undef; ir->accept(this); diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp index 184a2842093..7db5df403e0 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp @@ -106,7 +106,7 @@ fs_copy_prop_dataflow::fs_copy_prop_dataflow(void *mem_ctx, cfg_t *cfg, num_acp = 0; for (int b = 0; b < cfg->num_blocks; b++) { for (int i = 0; i < ACP_HASH_SIZE; i++) { - foreach_list(entry_node, &out_acp[b][i]) { + foreach_in_list(acp_entry, entry, &out_acp[b][i]) { num_acp++; } } @@ -124,9 +124,7 @@ fs_copy_prop_dataflow::fs_copy_prop_dataflow(void *mem_ctx, cfg_t *cfg, bd[b].kill = rzalloc_array(bd, BITSET_WORD, bitset_words); for (int i = 0; i < ACP_HASH_SIZE; i++) { - foreach_list(entry_node, &out_acp[b][i]) { - acp_entry *entry = (acp_entry *)entry_node; - + foreach_in_list(acp_entry, entry, &out_acp[b][i]) { acp[next_acp] = entry; /* opt_copy_propagate_local populates out_acp with copies created @@ -536,9 +534,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block, if (inst->src[i].file != GRF) continue; - foreach_list(entry_node, &acp[inst->src[i].reg % ACP_HASH_SIZE]) { - acp_entry *entry = (acp_entry *)entry_node; - + foreach_in_list(acp_entry, entry, &acp[inst->src[i].reg % ACP_HASH_SIZE]) { if (try_constant_propagate(brw, inst, entry)) progress = true; diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 3dab2dae0e4..703a2a47e8b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -84,8 +84,7 @@ fs_generator::patch_discard_jumps_to_fb_writes() int ip = p->nr_insn; - foreach_list(node, &this->discard_halt_patches) { - ip_record *patch_ip = (ip_record *)node; + foreach_in_list(ip_record, patch_ip, &discard_halt_patches) { brw_inst *patch = &p->store[patch_ip->ip]; assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT); @@ -1326,8 +1325,7 @@ fs_generator::generate_code(exec_list *instructions) if (unlikely(debug_flag)) cfg = new(mem_ctx) cfg_t(instructions); - foreach_list(node, instructions) { - fs_inst *inst = (fs_inst *)node; + foreach_in_list(fs_inst, inst, instructions) { struct brw_reg src[3], dst; unsigned int last_insn_offset = p->next_insn_offset; diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 4ff6f18ffde..3f273642200 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -54,9 +54,7 @@ fs_visitor::assign_regs_trivial() } this->grf_used = hw_reg_mapping[this->virtual_grf_count]; - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { assign_reg(hw_reg_mapping, &inst->dst, reg_width); assign_reg(hw_reg_mapping, &inst->src[0], reg_width); assign_reg(hw_reg_mapping, &inst->src[1], reg_width); @@ -241,9 +239,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g, int payload_last_use_ip[payload_node_count]; memset(payload_last_use_ip, 0, sizeof(payload_last_use_ip)); int ip = 0; - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { switch (inst->opcode) { case BRW_OPCODE_DO: loop_depth++; @@ -363,9 +359,7 @@ fs_visitor::get_used_mrfs(bool *mrf_used) memset(mrf_used, 0, BRW_MAX_MRF * sizeof(bool)); - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { if (inst->dst.file == MRF) { int reg = inst->dst.reg & ~BRW_MRF_COMPR4; mrf_used[reg] = true; @@ -522,9 +516,7 @@ fs_visitor::assign_regs(bool allow_spilling) reg_width); } - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { assign_reg(hw_reg_mapping, &inst->dst, reg_width); assign_reg(hw_reg_mapping, &inst->src[0], reg_width); assign_reg(hw_reg_mapping, &inst->src[1], reg_width); @@ -580,9 +572,7 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) * spill/unspill we'll have to do, and guess that the insides of * loops run 10 times. */ - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) { spill_costs[inst->src[i].reg] += loop_scale; @@ -679,9 +669,7 @@ fs_visitor::spill_reg(int spill_reg) * virtual grf of the same size. For most instructions, though, we * could just spill/unspill the GRF being accessed. */ - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg) { diff --git a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp index a740c58a162..7b2b0d11aec 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp @@ -133,8 +133,7 @@ can_coalesce_vars(brw::fs_live_variables *live_intervals, int scan_ip = -1; - foreach_list(n, instructions) { - fs_inst *scan_inst = (fs_inst *)n; + foreach_in_list(fs_inst, scan_inst, instructions) { scan_ip++; if (scan_inst->is_control_flow()) @@ -169,9 +168,7 @@ fs_visitor::register_coalesce() int var_to[MAX_SAMPLER_MESSAGE_SIZE]; int var_from[MAX_SAMPLER_MESSAGE_SIZE]; - foreach_list(node, &this->instructions) { - fs_inst *inst = (fs_inst *)node; - + foreach_in_list(fs_inst, inst, &instructions) { if (!is_coalesce_candidate(inst, virtual_grf_sizes)) continue; @@ -242,9 +239,7 @@ fs_visitor::register_coalesce() } } - foreach_list(node, &this->instructions) { - fs_inst *scan_inst = (fs_inst *)node; - + foreach_in_list(fs_inst, scan_inst, &instructions) { for (int i = 0; i < src_size; i++) { if (mov[i] || was_load_payload) { if (scan_inst->dst.file == GRF && diff --git a/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp b/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp index a9125cad8f9..a048b3dc0e5 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp @@ -121,8 +121,7 @@ ir_vector_reference_visitor::get_variable_entry(ir_variable *var) break; } - foreach_list(node, &this->variable_list) { - variable_entry *entry = (variable_entry *)node; + foreach_in_list(variable_entry, entry, &variable_list) { if (entry->var == var) return entry; } @@ -219,8 +218,7 @@ ir_vector_splitting_visitor::get_splitting_entry(ir_variable *var) if (!var->type->is_vector()) return NULL; - foreach_list(node, &*this->variable_list) { - variable_entry *entry = (variable_entry *)node; + foreach_in_list(variable_entry, entry, variable_list) { if (entry->var == var) { return entry; } @@ -360,8 +358,7 @@ brw_do_vector_splitting(exec_list *instructions) /* Replace the decls of the vectors to be split with their split * components. */ - foreach_list(node, &refs.variable_list) { - variable_entry *entry = (variable_entry *)node; + foreach_in_list(variable_entry, entry, &refs.variable_list) { const struct glsl_type *type; type = glsl_type::get_instance(entry->var->type->base_type, 1, 1); diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 654f5fec593..ce7075f7940 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -1970,8 +1970,7 @@ fs_visitor::visit(ir_constant *ir) } } } else if (ir->type->is_record()) { - foreach_list(node, &ir->components) { - ir_constant *const field = (ir_constant *) node; + foreach_in_list(ir_constant, field, &ir->components) { const unsigned size = type_size(field->type); field->accept(this); @@ -2260,21 +2259,17 @@ fs_visitor::visit(ir_if *ir) emit(IF(BRW_PREDICATE_NORMAL)); } - foreach_list(node, &ir->then_instructions) { - ir_instruction *ir = (ir_instruction *)node; - this->base_ir = ir; - - ir->accept(this); + foreach_in_list(ir_instruction, ir_, &ir->then_instructions) { + this->base_ir = ir_; + ir_->accept(this); } if (!ir->else_instructions.is_empty()) { emit(BRW_OPCODE_ELSE); - foreach_list(node, &ir->else_instructions) { - ir_instruction *ir = (ir_instruction *)node; - this->base_ir = ir; - - ir->accept(this); + foreach_in_list(ir_instruction, ir_, &ir->else_instructions) { + this->base_ir = ir_; + ir_->accept(this); } } @@ -2293,11 +2288,9 @@ fs_visitor::visit(ir_loop *ir) this->base_ir = NULL; emit(BRW_OPCODE_DO); - foreach_list(node, &ir->body_instructions) { - ir_instruction *ir = (ir_instruction *)node; - - this->base_ir = ir; - ir->accept(this); + foreach_in_list(ir_instruction, ir_, &ir->body_instructions) { + this->base_ir = ir_; + ir_->accept(this); } this->base_ir = NULL; @@ -2392,11 +2385,9 @@ fs_visitor::visit(ir_function *ir) assert(sig); - foreach_list(node, &sig->body) { - ir_instruction *ir = (ir_instruction *)node; - this->base_ir = ir; - - ir->accept(this); + foreach_in_list(ir_instruction, ir_, &sig->body) { + this->base_ir = ir_; + ir_->accept(this); } } } diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index 14f95791ae0..cc136a5b948 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -772,8 +772,7 @@ fs_instruction_scheduler::calculate_deps() memset(last_mrf_write, 0, sizeof(last_mrf_write)); /* top-to-bottom dependencies: RAW and WAW. */ - foreach_list(node, &instructions) { - schedule_node *n = (schedule_node *)node; + foreach_in_list(schedule_node, n, &instructions) { fs_inst *inst = (fs_inst *)n->inst; if (inst->opcode == FS_OPCODE_PLACEHOLDER_HALT || @@ -1035,8 +1034,7 @@ vec4_instruction_scheduler::calculate_deps() memset(last_mrf_write, 0, sizeof(last_mrf_write)); /* top-to-bottom dependencies: RAW and WAW. */ - foreach_list(node, &instructions) { - schedule_node *n = (schedule_node *)node; + foreach_in_list(schedule_node, n, &instructions) { vec4_instruction *inst = (vec4_instruction *)n->inst; if (inst->has_side_effects()) @@ -1215,9 +1213,7 @@ fs_instruction_scheduler::choose_instruction_to_schedule() /* Of the instructions ready to execute or the closest to * being ready, choose the oldest one. */ - foreach_list(node, &instructions) { - schedule_node *n = (schedule_node *)node; - + foreach_in_list(schedule_node, n, &instructions) { if (!chosen || n->unblocked_time < chosen_time) { chosen = n; chosen_time = n->unblocked_time; @@ -1230,8 +1226,7 @@ fs_instruction_scheduler::choose_instruction_to_schedule() * shaders which naturally do a better job of hiding instruction * latency. */ - foreach_list(node, &instructions) { - schedule_node *n = (schedule_node *)node; + foreach_in_list(schedule_node, n, &instructions) { fs_inst *inst = (fs_inst *)n->inst; if (!chosen) { @@ -1325,9 +1320,7 @@ vec4_instruction_scheduler::choose_instruction_to_schedule() /* Of the instructions ready to execute or the closest to being ready, * choose the oldest one. */ - foreach_list(node, &instructions) { - schedule_node *n = (schedule_node *)node; - + foreach_in_list(schedule_node, n, &instructions) { if (!chosen || n->unblocked_time < chosen_time) { chosen = n; chosen_time = n->unblocked_time; @@ -1426,9 +1419,7 @@ instruction_scheduler::schedule_instructions(backend_instruction *next_block_hea * is done. */ if (chosen->inst->is_math()) { - foreach_list(node, &instructions) { - schedule_node *n = (schedule_node *)node; - + foreach_in_list(schedule_node, n, &instructions) { if (n->inst->is_math()) n->unblocked_time = MAX2(n->unblocked_time, time + chosen->latency); @@ -1455,7 +1446,7 @@ instruction_scheduler::run(exec_list *all_instructions) * scheduling. */ if (remaining_grf_uses) { - foreach_list(node, all_instructions) { + foreach_in_list(schedule_node, node, all_instructions) { count_remaining_grf_uses((backend_instruction *)node); } } @@ -1472,8 +1463,7 @@ instruction_scheduler::run(exec_list *all_instructions) } calculate_deps(); - foreach_list(node, &instructions) { - schedule_node *n = (schedule_node *)node; + foreach_in_list(schedule_node, n, &instructions) { compute_delay(n); } diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 2fa3ad945df..e1e8f5e35ab 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -213,8 +213,8 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) * too late. At that point, the values for the built-in uniforms won't * get sent to the shader. */ - foreach_list(node, shader->base.ir) { - ir_variable *var = ((ir_instruction *) node)->as_variable(); + foreach_in_list(ir_instruction, node, shader->base.ir) { + ir_variable *var = node->as_variable(); if ((var == NULL) || (var->data.mode != ir_var_uniform) || (strncmp(var->name, "gl_", 3) != 0)) @@ -719,8 +719,7 @@ backend_visitor::dump_instructions(const char *name) } int ip = 0; - foreach_list(node, &this->instructions) { - backend_instruction *inst = (backend_instruction *)node; + foreach_in_list(backend_instruction, inst, &instructions) { if (!name) fprintf(stderr, "%d: ", ip++); dump_instruction(inst, file); diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 24903f952d1..bcd1b3a8a79 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -501,9 +501,7 @@ vec4_visitor::split_uniform_registers() * vector. The goal is to make elimination of unused uniform * components easier later. */ - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -536,9 +534,7 @@ vec4_visitor::pack_uniform_registers() * expect unused vector elements when we've moved array access out * to pull constants, and from some GLSL code generators like wine. */ - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -591,9 +587,7 @@ vec4_visitor::pack_uniform_registers() this->uniforms = new_uniform_count; /* Now, update the instructions for our repacked uniforms. */ - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { for (int i = 0 ; i < 3; i++) { int src = inst->src[i].reg; @@ -654,9 +648,7 @@ vec4_visitor::opt_algebraic() { bool progress = false; - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { switch (inst->opcode) { case BRW_OPCODE_ADD: if (inst->src[1].is_zero()) { @@ -1207,9 +1199,7 @@ vec4_visitor::split_virtual_grfs() /* Check that the instructions are compatible with the registers we're trying * to split. */ - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { /* If there's a SEND message loading from a GRF on gen7+, it needs to be * contiguous. */ @@ -1238,9 +1228,7 @@ vec4_visitor::split_virtual_grfs() this->virtual_grf_sizes[i] = 1; } - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { if (inst->dst.file == GRF && split_grf[inst->dst.reg] && inst->dst.reg_offset != 0) { inst->dst.reg = (new_virtual_grf[inst->dst.reg] + @@ -1459,9 +1447,7 @@ void vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map, bool interleaved) { - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { /* We have to support ATTR as a destination for GL_FIXED fixup. */ if (inst->dst.file == ATTR) { int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp index db6063c3bcc..a277f998e46 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp @@ -312,9 +312,7 @@ vec4_visitor::opt_copy_propagation() memset(&cur_value, 0, sizeof(cur_value)); - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { /* This pass only works on basic blocks. If there's flow * control, throw out all our information and start from * scratch. diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index 9e0e7bb105f..ef0e60767eb 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -1238,8 +1238,7 @@ vec4_generator::generate_code(exec_list *instructions) if (unlikely(debug_flag)) cfg = new(mem_ctx) cfg_t(instructions); - foreach_list(node, instructions) { - vec4_instruction *inst = (vec4_instruction *)node; + foreach_in_list(vec4_instruction, inst, instructions) { struct brw_reg src[3], dst; if (unlikely(debug_flag)) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp index 5f0b696bf1c..938ae4331a1 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp @@ -215,9 +215,7 @@ vec4_visitor::calculate_live_intervals() * flow. */ int ip = 0; - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { for (unsigned int i = 0; i < 3; i++) { if (inst->src[i].file == GRF) { int reg = inst->src[i].reg; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp index 349c031090c..4ffc537cc36 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp @@ -56,9 +56,7 @@ vec4_visitor::reg_allocate_trivial() virtual_grf_used[i] = false; } - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *) node; - + foreach_in_list(vec4_instruction, inst, &instructions) { if (inst->dst.file == GRF) virtual_grf_used[inst->dst.reg] = true; @@ -78,9 +76,7 @@ vec4_visitor::reg_allocate_trivial() } prog_data->total_grf = next; - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *) node; - + foreach_in_list(vec4_instruction, inst, &instructions) { assign(hw_reg_mapping, &inst->dst); assign(hw_reg_mapping, &inst->src[0]); assign(hw_reg_mapping, &inst->src[1]); @@ -241,9 +237,7 @@ vec4_visitor::reg_allocate() hw_reg_mapping[i] + virtual_grf_sizes[i]); } - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { assign(hw_reg_mapping, &inst->dst); assign(hw_reg_mapping, &inst->src[0]); assign(hw_reg_mapping, &inst->src[1]); @@ -269,9 +263,7 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) * spill/unspill we'll have to do, and guess that the insides of * loops run 10 times. */ - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *) node; - + foreach_in_list(vec4_instruction, inst, &instructions) { for (unsigned int i = 0; i < 3; i++) { if (inst->src[i].file == GRF) { spill_costs[inst->src[i].reg] += loop_scale; @@ -335,9 +327,7 @@ vec4_visitor::spill_reg(int spill_reg_nr) unsigned int spill_offset = c->last_scratch++; /* Generate spill/unspill instructions for the objects being spilled. */ - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *) node; - + foreach_in_list(vec4_instruction, inst, &instructions) { for (unsigned int i = 0; i < 3; i++) { if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) { src_reg spill_reg = inst->src[i]; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 219515a9c2a..dea7ae4bf1d 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -549,9 +549,7 @@ vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0) void vec4_visitor::visit_instructions(const exec_list *list) { - foreach_list(node, list) { - ir_instruction *ir = (ir_instruction *)node; - + foreach_in_list(ir_instruction, ir, list) { base_ir = ir; ir->accept(this); } @@ -2163,9 +2161,7 @@ void vec4_visitor::emit_constant_values(dst_reg *dst, ir_constant *ir) { if (ir->type->base_type == GLSL_TYPE_STRUCT) { - foreach_list(node, &ir->components) { - ir_constant *field_value = (ir_constant *)node; - + foreach_in_list(ir_constant, field_value, &ir->components) { emit_constant_values(dst, field_value); } return; @@ -3235,9 +3231,7 @@ vec4_visitor::move_grf_array_access_to_scratch() * to scratch due to having any array access on them, and where in * scratch. */ - foreach_list(node, &this->instructions) { - vec4_instruction *inst = (vec4_instruction *)node; - + foreach_in_list(vec4_instruction, inst, &instructions) { if (inst->dst.file == GRF && inst->dst.reladdr && scratch_loc[inst->dst.reg] == -1) { scratch_loc[inst->dst.reg] = c->last_scratch; diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp index ac8bf1d4ae4..fa895310e37 100644 --- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp @@ -663,8 +663,7 @@ gen8_fs_generator::patch_discard_jumps_to_fb_writes() int ip = nr_inst; - foreach_list(node, &discard_halt_patches) { - ip_record *patch_ip = (ip_record *) node; + foreach_in_list(ip_record, patch_ip, &discard_halt_patches) { gen8_instruction *patch = &store[patch_ip->ip]; assert(gen8_opcode(patch) == BRW_OPCODE_HALT); @@ -895,8 +894,7 @@ gen8_fs_generator::generate_code(exec_list *instructions) if (unlikely(INTEL_DEBUG & DEBUG_WM)) cfg = new(mem_ctx) cfg_t(instructions); - foreach_list(node, instructions) { - fs_inst *ir = (fs_inst *) node; + foreach_in_list(fs_inst, ir, instructions) { struct brw_reg src[3], dst; if (unlikely(INTEL_DEBUG & DEBUG_WM)) diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp index da6c8975f96..457e8003be7 100644 --- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp @@ -851,8 +851,7 @@ gen8_vec4_generator::generate_code(exec_list *instructions) if (unlikely(debug_flag)) cfg = new(mem_ctx) cfg_t(instructions); - foreach_list(node, instructions) { - vec4_instruction *ir = (vec4_instruction *) node; + foreach_in_list(vec4_instruction, ir, instructions) { struct brw_reg src[3], dst; if (unlikely(debug_flag))