From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 May 2021 13:15:49 +0000 (+0100)
Subject: add links to set associative image, and bugreport
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c51597dabb3af7e306bf6136215db4326a476e0d;p=soc.git

add links to set associative image, and bugreport
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 00c68685..65ed3465 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -8,6 +8,12 @@ see WB4 spec, p84, section 5.2.1
 
 IMPORTANT: for store, the data is sampled the cycle AFTER the "valid"
 is raised.  sigh
+
+Links:
+
+* https://libre-soc.org/3d_gpu/architecture/set_associative_cache.jpg
+* https://bugs.libre-soc.org/show_bug.cgi?id=469
+
 """
 
 import sys
@@ -579,6 +585,7 @@ class DCachePendingHit(Elaboratable):
 
 class DCache(Elaboratable):
     """Set associative dcache write-through
+
     TODO (in no specific order):
     * See list in icache.vhdl
     * Complete load misses on the cycle when WB data comes instead of