From: Clifford Wolf Date: Sat, 4 Apr 2015 17:00:15 +0000 (+0200) Subject: Added "dffinit", Support for initialized Xilinx DFF X-Git-Tag: yosys-0.6~362 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c52a4cdeede6904f9b0d91a61a3fbeaade71a46a;p=yosys.git Added "dffinit", Support for initialized Xilinx DFF --- diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1d0008f9d..702addd7e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -474,6 +474,7 @@ struct RTLIL::Const std::string decode_string() const; inline int size() const { return bits.size(); } + inline RTLIL::State operator[](int index) { return bits.at(index); } inline unsigned int hash() const { unsigned int h = mkhash_init; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a393343d1..571770328 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -510,7 +510,7 @@ struct HierarchyPass : public Pass { if (top_mod == nullptr && auto_top_mode) { log_header("Finding top of design hierarchy..\n"); dict db; - for (Module *mod : design->modules()) { + for (Module *mod : design->selected_modules()) { int score = find_top_mod_score(design, mod, db); log("root of %3d design levels: %-20s\n", score, log_id(mod)); if (!top_mod || score > db[top_mod]) @@ -613,5 +613,5 @@ struct HierarchyPass : public Pass { log_pop(); } } HierarchyPass; - + PRIVATE_NAMESPACE_END diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 6b6846e20..7c1ec884c 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -11,6 +11,7 @@ OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/extract.o OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/dff2dffe.o +OBJS += passes/techmap/dffinit.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 17549bd06..da6060564 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -255,7 +255,7 @@ struct Dff2dffePass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" dff2dffe [selection]\n"); + log(" dff2dffe [options] [selection]\n"); log("\n"); log("This pass transforms $dff cells driven by a tree of multiplexers with one or\n"); log("more feedback paths to $dffe cells. It also works on gate-level cells such as\n"); diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc new file mode 100644 index 000000000..3317e8afb --- /dev/null +++ b/passes/techmap/dffinit.cc @@ -0,0 +1,121 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct DffinitPass : public Pass { + DffinitPass() : Pass("dffinit", "set INIT param on FF cells") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" dffinit [options] [selection]\n"); + log("\n"); + log("This pass sets an FF cell parameter to the the initial value of the net it\n"); + log("drives. (This is primarily used in FPGA flows.)\n"); + log("\n"); + log(" -ff \n"); + log(" operate on the specified cell type. this option can be used\n"); + log(" multiple times.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + log_header("Executing DFFINIT pass (set INIT param on FF cells).\n"); + + dict> ff_types; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-ff" && argidx+3 < args.size()) { + IdString cell_name = RTLIL::escape_id(args[++argidx]); + IdString output_port = RTLIL::escape_id(args[++argidx]); + IdString init_param = RTLIL::escape_id(args[++argidx]); + ff_types[cell_name][output_port] = init_param; + continue; + } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + SigMap sigmap(module); + dict init_bits; + pool cleanup_bits; + + for (auto wire : module->selected_wires()) + if (wire->attributes.count("\\init")) { + Const value = wire->attributes.at("\\init"); + for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) + init_bits[sigmap(SigBit(wire, i))] = value[i]; + } + + for (auto cell : module->selected_cells()) + { + if (ff_types.count(cell->type) == 0) + continue; + + for (auto &it : ff_types[cell->type]) + { + if (!cell->hasPort(it.first)) + continue; + + SigSpec sig = sigmap(cell->getPort(it.first)); + Const value; + + if (cell->hasParam(it.second)) + value = cell->getParam(it.second); + + for (int i = 0; i < GetSize(sig); i++) { + if (init_bits.count(sig[i]) == 0) + continue; + while (GetSize(value.bits) < i) + value.bits.push_back(State::S0); + value.bits[i] = init_bits.at(sig[i]); + cleanup_bits.insert(sig[i]); + } + + log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second), + log_id(it.first), log_signal(sig), log_signal(value)); + cell->setParam(it.second, value); + } + } + + for (auto wire : module->selected_wires()) + if (wire->attributes.count("\\init")) { + Const value = wire->attributes.at("\\init"); + bool do_cleanup = true; + for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) + if (cleanup_bits.count(sigmap(SigBit(wire, i))) == 0) + do_cleanup = false; + if (do_cleanup) { + log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); + wire->attributes.erase("\\init"); + } + } + } + } +} DffinitPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 836ba9add..8aebf3026 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -47,7 +47,7 @@ struct SynthXilinxPass : public Pass { log("compatible with 7-Series Xilinx devices.\n"); log("\n"); log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); + log(" use the specified module as top module\n"); log("\n"); log(" -edif \n"); log(" write the design to the specified edif file. writing of an output file\n"); @@ -96,6 +96,7 @@ struct SynthXilinxPass : public Pass { log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); + log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n"); log(" clean\n"); log("\n"); log(" check:\n"); @@ -109,8 +110,7 @@ struct SynthXilinxPass : public Pass { } virtual void execute(std::vector args, RTLIL::Design *design) { - std::string top_module = "top"; - std::string arch_name = "spartan6"; + std::string top_opt = "-auto-top"; std::string edif_file; std::string run_from, run_to; bool flatten = false; @@ -120,7 +120,7 @@ struct SynthXilinxPass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-top" && argidx+1 < args.size()) { - top_module = args[++argidx]; + top_opt = "-top " + args[++argidx]; continue; } if (args[argidx] == "-edif" && argidx+1 < args.size()) { @@ -158,7 +158,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "begin")) { Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); - Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str())); + Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); } if (flatten && check_label(active, run_from, run_to, "flatten")) @@ -197,6 +197,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); Pass::call(design, "clean"); }