From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 15 Apr 2020 22:50:57 +0000 (-0700)
Subject: abc9_ops: more robust
X-Git-Tag: working-ls180~549^2~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c52bb11fb6a4a34ba702e35c2950efb978b953ad;p=yosys.git

abc9_ops: more robust
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index e00a4dc81..544fefdfb 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -641,7 +641,8 @@ void prep_box(RTLIL::Design *design)
 			log_assert(num_outputs == 1);
 
 			ss << log_id(module) << " " << r.first->second.as_int();
-			ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+			log_assert(module->get_bool_attribute(ID::whitebox));
+			ss << " " << "1";
 			ss << " " << num_inputs << " " << num_outputs << std::endl;
 
 			ss << "#";
@@ -659,6 +660,9 @@ void prep_box(RTLIL::Design *design)
 			ss << std::endl;
 
 			auto &t = timing.setup_module(module).required;
+			if (t.empty())
+				log_error("Module '%s' with (* abc9_flop *) has no clk-to-q timing (and thus no connectivity) information.\n", log_id(module));
+
 			first = true;
 			for (auto port_name : module->ports) {
 				auto wire = module->wire(port_name);
@@ -671,8 +675,8 @@ void prep_box(RTLIL::Design *design)
 				log_assert(GetSize(wire) == 1);
 				auto it = t.find(TimingInfo::NameBit(port_name,0));
 				if (it == t.end())
-					// Assume that no setup time means zero
-					ss << 0;
+					// Assume no connectivity if no setup time
+					ss << "-";
 				else {
 					ss << it->second;
 
@@ -743,9 +747,11 @@ void prep_box(RTLIL::Design *design)
 			}
 			ss << std::endl;
 
-			auto &t = timing.setup_module(module).comb;
-			if (t.empty())
-				log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
+			auto &t = timing.setup_module(module);
+			if (t.comb.empty())
+				log_error("Module '%s' with (* abc9_box *) has no timing (and thus no connectivity) information.\n", log_id(module));
+			if (!t.arrival.empty() || !t.required.empty())
+				log_error("Module '%s' with (* abc9_box *) has setup and/or edge-sensitive timing information.\n", log_id(module));
 
 			for (const auto &o : outputs) {
 				first = true;
@@ -754,8 +760,8 @@ void prep_box(RTLIL::Design *design)
 						first = false;
 					else
 						ss << " ";
-					auto jt = t.find(TimingInfo::BitBit(i,o));
-					if (jt == t.end())
+					auto jt = t.comb.find(TimingInfo::BitBit(i,o));
+					if (jt == t.comb.end())
 						ss << "-";
 					else
 						ss << jt->second;