From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Nov 2021 19:01:40 +0000 (+0000)
Subject: allow MSR to be set in StateRegs in test_core.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c53977293f3c536e097abd689c53afd25da97d16;p=soc.git

allow MSR to be set in StateRegs in test_core.py
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index c15732d1..dfafb2cb 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -42,6 +42,8 @@ from soc.fu.branch.test.test_pipe_caller import BranchTestCase
 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
 from openpower.util import spr_to_fast_reg
 
+from openpower.consts import StateRegsEnum
+
 # list of SPRs that are controlled and managed by the MMU
 mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
 
@@ -67,6 +69,10 @@ def setup_regs(pdecode2, core, test):
             yield intregs.memory._array[i].eq(test.regs[i])
     yield Settle()
 
+    # set up MSR in STATE regfile, "direct" write (bypass rd/write ports)
+    stateregs = core.regs.state
+    yield stateregs.regs[StateRegsEnum.MSR].reg.eq(test.msr)
+
     # set up CR regfile, "direct" write across all CRs
     cr = test.cr
     crregs = core.regs.cr