From: Uros Bizjak <ubizjak@gmail.com>
Date: Tue, 21 May 2019 16:00:37 +0000 (+0200)
Subject: sse.md (VF1_AVX2): New mode iterator.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c54eb7f40ce09bc22aca2aea7cdde6e286249ada;p=gcc.git

sse.md (VF1_AVX2): New mode iterator.

	* config/i386/sse.md (VF1_AVX2): New mode iterator.
	(signbit<mode>2): New expander

testsuite/ChangeLog:

	* gcc.target/i386/vect-signbitf.c: New test.

From-SVN: r271473
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 23b9b117445..0651fbabed2 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-05-21  Uroš Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/sse.md (VF1_AVX2): New mode iterator.
+	(signbit<mode>2): New expander
+
 2019-05-21  James Clarke  <jrtc27@jrtc27.com>
 
 	PR bootstrap/87338
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 677e7023eb2..7e7b3417cfc 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -279,6 +279,9 @@
 (define_mode_iterator VF1
   [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF])
 
+(define_mode_iterator VF1_AVX2
+  [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX2") V4SF])
+
 ;; 128- and 256-bit SF vector modes
 (define_mode_iterator VF1_128_256
   [(V8SF "TARGET_AVX") V4SF])
@@ -3523,6 +3526,15 @@
   operands[4] = gen_reg_rtx (<MODE>mode);
 })
 
+(define_expand "signbit<mode>2"
+  [(set (match_operand:<sseintvecmode> 0 "register_operand")
+	(lshiftrt:<sseintvecmode>
+	  (subreg:<sseintvecmode>
+	    (match_operand:VF1_AVX2 1 "register_operand") 0)
+	  (match_dup 2)))]
+  "TARGET_SSE2"
+  "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);")
+
 ;; Also define scalar versions.  These are used for abs, neg, and
 ;; conditional move.  Using subregs into vector modes causes register
 ;; allocation lossage.  These patterns do not allow memory operands
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index bdc58ba14e4..6206ef52c4a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-05-21  Uroš Bizjak  <ubizjak@gmail.com>
+
+	* gcc.target/i386/vect-signbitf.c: New test.
+
 2019-05-21  Nathan Sidwell  <nathan@acm.org>
 
 	* g++.dg/lookup/using53.C: Adjust diagnostic.
diff --git a/gcc/testsuite/gcc.target/i386/vect-signbitf.c b/gcc/testsuite/gcc.target/i386/vect-signbitf.c
new file mode 100644
index 00000000000..b3ef1062c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-signbitf.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target sse2_runtime } } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
+
+extern void abort ();
+
+#define N 1024
+float a[N] = {0.0f, -0.0f, 1.0f, -1.0f,
+	      -2.0f, 3.0f, -5.0f, -8.0f,
+	      13.0f, 21.0f, -25.0f, 33.0f};
+int r[N];
+
+int
+main (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    r[i] = __builtin_signbitf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    if (__builtin_signbit (a[i]) && !r[i])
+      abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-assembler-not "-2147483648" } } */
+/* { dg-final { scan-assembler "psrld" } } */