From: Emily Brickey Date: Tue, 18 Aug 2020 20:16:53 +0000 (-0700) Subject: arch-riscv, arch-x86: convert tlb to new style stats X-Git-Tag: v20.1.0.0~255 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5522f2b324bd01b0fd75174886e433dd7d3deb6;p=gem5.git arch-riscv, arch-x86: convert tlb to new style stats Change-Id: Ie2754d861a658fde0acdda30cbcb91e02029e33a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32835 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc index c8b1a4c6f..34ccc0375 100644 --- a/src/arch/riscv/tlb.cc +++ b/src/arch/riscv/tlb.cc @@ -66,7 +66,7 @@ buildKey(Addr vpn, uint16_t asid) } TLB::TLB(const Params *p) - : BaseTLB(p), size(p->size), tlb(size), lruSeq(0) + : BaseTLB(p), size(p->size), tlb(size), lruSeq(0), stats(this) { for (size_t x = 0; x < size; x++) { tlb[x].trieHandle = NULL; @@ -108,21 +108,21 @@ TLB::lookup(Addr vpn, uint16_t asid, Mode mode, bool hidden) entry->lruSeq = nextSeq(); if (mode == Write) - write_accesses++; + stats.write_accesses++; else - read_accesses++; + stats.read_accesses++; if (!entry) { if (mode == Write) - write_misses++; + stats.write_misses++; else - read_misses++; + stats.read_misses++; } else { if (mode == Write) - write_hits++; + stats.write_hits++; else - read_hits++; + stats.read_hits++; } DPRINTF(TLBVerbose, "lookup(vpn=%#x, asid=%#x): %s ppn %#x\n", @@ -496,61 +496,20 @@ TLB::unserialize(CheckpointIn &cp) } } -void -TLB::regStats() +TLB::TlbStats::TlbStats(Stats::Group *parent) + : Stats::Group(parent), + ADD_STAT(read_hits, "read hits"), + ADD_STAT(read_misses, "read misses"), + ADD_STAT(read_accesses, "read accesses"), + ADD_STAT(write_hits, "write hits"), + ADD_STAT(write_misses, "write misses"), + ADD_STAT(write_accesses, "write accesses"), + ADD_STAT(hits, "Total TLB (read and write) hits", read_hits + write_hits), + ADD_STAT(misses, "Total TLB (read and write) misses", + read_misses + write_misses), + ADD_STAT(accesses, "Total TLB (read and write) accesses", + read_accesses + write_accesses) { - BaseTLB::regStats(); - - read_hits - .name(name() + ".read_hits") - .desc("DTB read hits") - ; - - read_misses - .name(name() + ".read_misses") - .desc("DTB read misses") - ; - - - read_accesses - .name(name() + ".read_accesses") - .desc("DTB read accesses") - ; - - write_hits - .name(name() + ".write_hits") - .desc("DTB write hits") - ; - - write_misses - .name(name() + ".write_misses") - .desc("DTB write misses") - ; - - - write_accesses - .name(name() + ".write_accesses") - .desc("DTB write accesses") - ; - - hits - .name(name() + ".hits") - .desc("DTB hits") - ; - - misses - .name(name() + ".misses") - .desc("DTB misses") - ; - - accesses - .name(name() + ".accesses") - .desc("DTB accesses") - ; - - hits = read_hits + write_hits; - misses = read_misses + write_misses; - accesses = read_accesses + write_accesses; } RiscvISA::TLB * diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh index 7ed662817..a92bdd2c1 100644 --- a/src/arch/riscv/tlb.hh +++ b/src/arch/riscv/tlb.hh @@ -52,7 +52,7 @@ namespace RiscvISA { class Walker; class TLB : public BaseTLB -{ + { typedef std::list EntryList; protected: @@ -64,17 +64,22 @@ class TLB : public BaseTLB Walker *walker; - mutable Stats::Scalar read_hits; - mutable Stats::Scalar read_misses; - mutable Stats::Scalar read_acv; - mutable Stats::Scalar read_accesses; - mutable Stats::Scalar write_hits; - mutable Stats::Scalar write_misses; - mutable Stats::Scalar write_acv; - mutable Stats::Scalar write_accesses; - Stats::Formula hits; - Stats::Formula misses; - Stats::Formula accesses; + struct TlbStats : public Stats::Group{ + TlbStats(Stats::Group *parent); + + Stats::Scalar read_hits; + Stats::Scalar read_misses; + Stats::Scalar read_acv; + Stats::Scalar read_accesses; + Stats::Scalar write_hits; + Stats::Scalar write_misses; + Stats::Scalar write_acv; + Stats::Scalar write_accesses; + + Stats::Formula hits; + Stats::Formula misses; + Stats::Formula accesses; + } stats; public: typedef RiscvTLBParams Params; @@ -98,8 +103,6 @@ class TLB : public BaseTLB void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; - void regStats() override; - Addr translateWithTLB(Addr vaddr, uint16_t asid, Mode mode); Fault translateAtomic(const RequestPtr &req, diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 4e9d4be25..11ce66062 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -61,7 +61,7 @@ namespace X86ISA { TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size), - tlb(size), lruSeq(0), m5opRange(p->system->m5opRange()) + tlb(size), lruSeq(0), m5opRange(p->system->m5opRange()), stats(this) { if (!size) fatal("TLBs must have a non-zero size.\n"); @@ -373,18 +373,18 @@ TLB::translate(const RequestPtr &req, // The vaddr already has the segment base applied. TlbEntry *entry = lookup(vaddr); if (mode == Read) { - rdAccesses++; + stats.rdAccesses++; } else { - wrAccesses++; + stats.wrAccesses++; } if (!entry) { DPRINTF(TLB, "Handling a TLB miss for " "address %#x at pc %#x.\n", vaddr, tc->instAddr()); if (mode == Read) { - rdMisses++; + stats.rdMisses++; } else { - wrMisses++; + stats.wrMisses++; } if (FullSystem) { Fault fault = walker->start(tc, translation, req, mode); @@ -518,27 +518,13 @@ TLB::getWalker() return walker; } -void -TLB::regStats() +TLB::TlbStats::TlbStats(Stats::Group *parent) + : Stats::Group(parent), + ADD_STAT(rdAccesses, "TLB accesses on read requests"), + ADD_STAT(wrAccesses, "TLB accesses on write requests"), + ADD_STAT(rdMisses, "TLB misses on read requests"), + ADD_STAT(wrMisses, "TLB misses on write requests") { - using namespace Stats; - BaseTLB::regStats(); - rdAccesses - .name(name() + ".rdAccesses") - .desc("TLB accesses on read requests"); - - wrAccesses - .name(name() + ".wrAccesses") - .desc("TLB accesses on write requests"); - - rdMisses - .name(name() + ".rdMisses") - .desc("TLB misses on read requests"); - - wrMisses - .name(name() + ".wrMisses") - .desc("TLB misses on write requests"); - } void diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 2a8cabfb3..671b16518 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -101,11 +101,14 @@ namespace X86ISA AddrRange m5opRange; - // Statistics - Stats::Scalar rdAccesses; - Stats::Scalar wrAccesses; - Stats::Scalar rdMisses; - Stats::Scalar wrMisses; + struct TlbStats : public Stats::Group { + TlbStats(Stats::Group *parent); + + Stats::Scalar rdAccesses; + Stats::Scalar wrAccesses; + Stats::Scalar rdMisses; + Stats::Scalar wrMisses; + } stats; Fault translateInt(bool read, RequestPtr req, ThreadContext *tc); @@ -149,11 +152,6 @@ namespace X86ISA TlbEntry *insert(Addr vpn, const TlbEntry &entry); - /* - * Function to register Stats - */ - void regStats() override; - // Checkpointing void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override;