From: Yvan Roux Date: Mon, 27 Apr 2015 09:08:11 +0000 (+0000) Subject: arm.md (*arm_subsi3_insn): Fixed redundant alternatives. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c55d8b0bee698146ce282ae28d1101a5a3a30a7b;p=gcc.git arm.md (*arm_subsi3_insn): Fixed redundant alternatives. 2015-04-27 Yvan Roux * config/arm/arm.md (*arm_subsi3_insn): Fixed redundant alternatives. From-SVN: r222453 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aae757566c6..3ec5aa74ab5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-04-27 Yvan Roux + + * config/arm/arm.md (*arm_subsi3_insn): Fixed redundant + alternatives. + 2015-04-26 Tom de Vries PR tree-optimization/65826 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 85d27d93a58..57b95bf1814 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1177,9 +1177,9 @@ ; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r ,r,r,rk,r") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,rI,r,r,k ,?n") - (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r ,I,r,r ,r")))] + [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r,r,r,rk,r") + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,I,r,r,k ,?n") + (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r,I,r,r ,r")))] "TARGET_32BIT" "@ sub%?\\t%0, %1, %2