From: Jacob Lifshay Date: Tue, 16 Jan 2024 18:39:20 +0000 (-0800) Subject: fill in my section of meeting X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c56ae4a7e8ecf94473166087fc40ec01b875295b;p=libreriscv.git fill in my section of meeting --- diff --git a/meetings/sync_up/sync_up_2024-01-16.mdwn b/meetings/sync_up/sync_up_2024-01-16.mdwn index 9067626c8..d7b8894ab 100644 --- a/meetings/sync_up/sync_up_2024-01-16.mdwn +++ b/meetings/sync_up/sync_up_2024-01-16.mdwn @@ -146,25 +146,8 @@ Announcement on # Jacob -- so, not a whole lot of news from me, i fixed a -extra-parenthesis-in-a-wrong-spot bug for dmitry and fixed a bug -luke left, but didn't actually make any coding progress beyond -that. - -During call, walked with Sadoon through assembler: - -``` -summary: discussing how to best split into sub-word chunks -for poly1305 -> tbh dsrd isn't better than other shifts here -It did help with taking the shift remainders and stitching them together which shortened the code quite a bit -Also considering doing sv.dsrd instead of two dsrd's since we already use setvl=2 here -> sv.dsrd is 8 bytes, just like 2x dsrd -But it's a good demo of setvl anyways -> yeah, being a good demo doesn't mean there isn't a better demo -The better demo is the mul/adds 😃 -> try using a different register than r0, the simulator may be treating that like (RA|0) and just using r0 in both iterations... -``` +- not a whole lot, will start working on presentation, helped resolve issue with luke & dmitry, fixed some bugs for dmitry. +- suggested that presentations should be submitted much closer to fosdem (few days), since 2 weeks is too early. I will not be ready by 2 weeks before. # Sadoon