From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 08:33:46 +0000 (+0100)
Subject: add comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c56fd1f7d4d9dfefe70453326842e4355390abcb;p=riscv-isa-sim.git

add comments
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 4766a82..b47cc7d 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -178,6 +178,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
     if (!zeroingsrc)
     {
+      // skip over masked-out elements in the src reg
       while ((src_pset = (src_pred & (1<<pred_remap(src_preg, *src_offs))))
                         == 0) {
           inc_offs(vlen, subvl, *src_offs, *ssv_offs);
@@ -188,6 +189,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
     }
     if (!zeroing)
     {
+      // skip over masked-out elements in the dest reg
       while ((dest_pset = (dest_pred & (1<<pred_remap(dest_preg, *dest_offs))))
                         == 0) {
           inc_offs(vlen, subvl, *dest_offs, *sub_doffs);