From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Feb 2024 14:39:12 +0000 (+0000)
Subject: bug 1034: invert ordering of lut indices to match xxeval
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c58f6099a;p=openpower-isa.git

bug 1034: invert ordering of lut indices to match xxeval
---

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index b2a0acc4..bd925d6a 100644
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -33,7 +33,7 @@ Pseudo-code:
     result <- [0] * XLEN
     do i = 0 to XLEN - 1
       idx <- (RT)[i] || (RA)[i] || (RB)[i]
-      result[i] <- TLI[7-idx]
+      result[i] <- TLI[idx]
     RT <- result
 
 Special Registers Altered:
@@ -53,7 +53,7 @@ Pseudo-code:
     result <- [0] * 64
     do i = 0 to 63
       idx <- (RA)[i] || (RB)[i]
-      result[i] <- lut[3-idx]
+      result[i] <- lut[idx]
     RT <- result
 
 Description:
@@ -86,7 +86,7 @@ Pseudo-code:
     result <- [0] * 4
     do i = 0 to 3
       idx <- bf[i] || bfa[i] || bfb[i]
-      result[i] <- TLI[7-idx]
+      result[i] <- TLI[idx]
     do i = 0 to 3
         if msk[i] = 1 then
             CR[4*BF+32+i] <- result[i]
@@ -104,7 +104,7 @@ TLI-Form
 Pseudo-code:
 
     idx <- CR[BT+32] || CR[BA+32] || CR[BB+32]
-    CR[BT+32] <- TLI[7-idx]
+    CR[BT+32] <- TLI[idx]
 
 Special Registers Altered:
 
@@ -125,7 +125,7 @@ Pseudo-code:
     result <- [0] * 4
     do i = 0 to 3
       idx <- a[i] || b[i]
-      result[i] <- lut[3-idx]
+      result[i] <- lut[idx]
     do i = 0 to 3
         if msk[i] = 1 then
             CR[4*BF+32+i] <- result[i]
@@ -159,7 +159,7 @@ Pseudo-code:
 
     lut <- CR[4*BFB+32:4*BFB+35]
     idx <- CR[BT+32] || CR[BA+32]
-    CR[BT+32] <- lut[3-idx]
+    CR[BT+32] <- lut[idx]
 
 Special registers altered:
 
diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py
index fb9e12fb..2e79931f 100644
--- a/src/openpower/test/bitmanip/bitmanip_cases.py
+++ b/src/openpower/test/bitmanip/bitmanip_cases.py
@@ -28,6 +28,7 @@ def crfbinlog(bf, bfa, bfb, mask):
             if check & (1<<i):
                 lut_index |= 1<<j
         maskbit = (mask >> i) & 0b1
+        lut_index = 3-lut_index # MSB0 inversion
         if (lut & (1<<lut_index)) and maskbit:
             expected |= 1<<i
     return expected
@@ -38,11 +39,11 @@ def ternlogi(rc, rt, ra, rb, imm):
     for i in range(64):
         lut_index = 0
         if rb & 2 ** i:
-            lut_index |= 2 ** 0
+            lut_index |= 2 ** 2
         if ra & 2 ** i:
             lut_index |= 2 ** 1
         if rt & 2 ** i:
-            lut_index |= 2 ** 2
+            lut_index |= 2 ** 0
         if imm & 2 ** lut_index:
             expected |= 2 ** i
     return expected
@@ -55,6 +56,7 @@ def crternlogi(bt, ba, bb, imm):
     for j, check in enumerate(checks):
         if check & 1:
             lut_index |= 1<<j
+    lut_index = 7-lut_index # MSB0 inversion
     if imm & (1<<lut_index):
         expected |= 1
     return expected
@@ -69,6 +71,7 @@ def crfternlogi(bf, bfa, bfb, imm, mask):
             if check & (1<<i):
                 lut_index |= 1<<j
         maskbit = (mask >> i) & 0b1
+        lut_index = 7-lut_index # MSB0 inversion
         if (imm & (1<<lut_index)) and maskbit:
             expected |= 1<<i
     return expected
@@ -216,6 +219,7 @@ class BitManipTestCase(TestAccumulatorBase):
                 lut_index |= 2 ** 1
             if rt & 2 ** i:
                 lut_index |= 2 ** 2
+            lut_index = 7-lut_index # MSB0 inversion
             if imm & 2 ** lut_index:
                 expected |= 2 ** i
         e.intregs[3] = expected
@@ -249,6 +253,7 @@ class BitManipTestCase(TestAccumulatorBase):
                 lut_index |= 2 ** 0
             if ra & 2 ** i:
                 lut_index |= 2 ** 1
+            lut_index = 3-lut_index # MSB0 inversion
             if lut & 2 ** lut_index:
                 expected |= 2 ** i
         e.intregs[3] = expected