From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Apr 2021 08:52:22 +0000 (+0100)
Subject: whoops should be cyc & ~ack
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c59d1a44683b54de2ea9577a03a00dbb9eb10f87;p=soc.git

whoops should be cyc & ~ack
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 09c907b5..4500d55f 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1625,7 +1625,7 @@ class DCache(Elaboratable):
         comb += self.wb_out.adr.eq(r1.wb.adr[3:]) # truncate LSBs
 
         # deal with litex not doing wishbone pipeline mode
-        comb += self.wb_in.stall.eq(self.wb_out.cyc & self.wb_in.ack)
+        comb += self.wb_in.stall.eq(self.wb_out.cyc & ~self.wb_in.ack)
 
         # call sub-functions putting everything together, using shared
         # signals established above