From: lkcl <lkcl@web>
Date: Sun, 25 Sep 2022 00:26:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~297
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5b8771d63f45991cb796e90790477faa3ff66d8;p=libreriscv.git

---

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index dd673a7c2..f63980cb1 100644
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -289,4 +289,6 @@ The reason why **GPR(3)** contains the value 0x200 (1<<9) when
 it was the 2nd Vector Element being written to is because of
 the sequential conceptual overlap between **all** registers, as
 ultimately the regfile must be considered arbitrarily-byte-addressable
-just like any Memory.
+just like any Memory, and therefore writing to
+half-word element `e4` starting from **GPR(2)** actually wrote to
+half-word element `e0` of GPR(3).