From: Luke Kenneth Casson Leighton Date: Wed, 17 Mar 2021 22:29:07 +0000 (+0000) Subject: re-enable SVP64 ISACaller predicate tests X-Git-Tag: convert-csv-opcode-to-binary~8 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5bde1fe8a106d9a52799e474f7fd1300a231f83;p=soc.git re-enable SVP64 ISACaller predicate tests --- diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py index cd4df1e9..afd50141 100644 --- a/src/soc/decoder/isa/test_caller_svp64_predication.py +++ b/src/soc/decoder/isa/test_caller_svp64_predication.py @@ -88,7 +88,7 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate) self._check_regs(sim, expected_regs) - def tst_sv_add_intpred(self): + def test_sv_add_intpred(self): # adds, integer predicated mask r3=0b10 # 1 = 5 + 9 => not to be touched (skipped) # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 @@ -119,7 +119,7 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate) self._check_regs(sim, expected_regs) - def tst_sv_add_cr_pred(self): + def test_sv_add_cr_pred(self): # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne) # 1 = 5 + 9 => not to be touched (skipped) # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111