From: whitequark <whitequark@whitequark.org>
Date: Fri, 9 Apr 2021 09:46:53 +0000 (+0000)
Subject: flatten: rewrite memid in memwr actions.
X-Git-Tag: yosys-0.10~220^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5c57e3f5e169aa13bf4f8ce064d7dc3a53616d7;p=yosys.git

flatten: rewrite memid in memwr actions.
---

diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc
index f35b7ff60..0509eedb8 100644
--- a/passes/techmap/flatten.cc
+++ b/passes/techmap/flatten.cc
@@ -122,6 +122,9 @@ struct FlattenWorker
 		for (auto &tpl_proc_it : tpl->processes) {
 			RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second);
 			map_attributes(cell, new_proc, tpl_proc_it.second->name);
+			for (auto new_proc_sync : new_proc->syncs)
+				for (auto &memwr_action : new_proc_sync->mem_write_actions)
+					memwr_action.memid = memory_map.at(memwr_action.memid).str();
 			auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); };
 			new_proc->rewrite_sigspecs(rewriter);
 			design->select(module, new_proc);