From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Jul 2020 20:01:04 +0000 (+0100)
Subject: add pspec to test_core.py
X-Git-Tag: div_pipeline~162^2~78
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5d28f6514c2e19dfd54f9861d03acfb7a51dd8f;p=soc.git

add pspec to test_core.py
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 322661e7..904aa76d 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -164,7 +164,13 @@ class TestRunner(FHDLTestCase):
         instruction = Signal(32)
         ivalid_i = Signal()
 
-        m.submodules.core = core = NonProductionCore()
+        pspec = TestMemPspec(ldst_ifacetype='testpi',
+                             imem_ifacetype='',
+                             addr_wid=48,
+                             mask_wid=8,
+                             reg_wid=64)
+
+        m.submodules.core = core = NonProductionCore(pspec)
         pdecode2 = core.pdecode2
         l0 = core.l0