From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 7 Jun 2018 09:50:04 +0000 (+0100)
Subject: clarify
X-Git-Tag: convert-csv-opcode-to-binary~5254
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5e65131c3ffbcad707d5e7c7283cf713eca1e4e;p=libreriscv.git

clarify
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 1b99f95cd..7017060fd 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -105,11 +105,11 @@
    \item Amazingly, SIMD becomes (more) tolerable\\
 	     (corner-cases for setup and teardown are gone)
    \item Modularity/Abstraction in both the h/w and the toolchain.
+   \item "Reach" of registers accessible by Compressed is enhanced
   \end{itemize}
   Note:
    \begin{itemize}
    \item It's not just about Vectors: it's about instruction effectiveness
-   \item Anything that makes SIMD tolerable has to be a good thing
    \item Anything implementor is not interested in HW-optimising,\\
 	     let it fall through to exceptions (implement as a trap).
   \end{itemize}