From: Luke Kenneth Casson Leighton Date: Sat, 19 Mar 2022 12:37:33 +0000 (+0000) Subject: fixed hyperram pin names which was stopping verilator (and pretty much X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5ec576e7c383ac0816cfb08052bae1c121b3ee9;p=ls2.git fixed hyperram pin names which was stopping verilator (and pretty much everything) from working. HyperRAMResource had a name "clk" as a pin which was obviously getting merged with sys_clk, sigh --- diff --git a/src/ls2.py b/src/ls2.py index 4f63cc3..c664ccc 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -406,7 +406,8 @@ class DDR3SoC(SoC, Elaboratable): # Esden, sold by 1bitsquared, only doing one CS_N enable at the # moment if hyperram_pins is not None: - self.hyperram = HyperRAM(io=hyperram_pins, phy_kls=HyperRAMPHY) + self.hyperram = HyperRAM(io=hyperram_pins, phy_kls=HyperRAMPHY, + features={'stall'}) self._decoder.add(self.hyperram.bus, addr=hyperram_addr) self.memory_map = self._decoder.bus.memory_map @@ -618,16 +619,13 @@ if __name__ == "__main__": if platform is not None and fpga in ['versa_ecp5']: hyperram_ios = HyperRAMResources(cs_n="B1", dq="D0 D1 D2 D3 D4 D7 D6 D7", - rwds="B2", rst_n="B3", clk_p="B4", + rwds="B2", rst_n="B3", ck_p="B4", attrs=IOStandard("LVCMOS33")) self.platform.add_extension(hyperram_ios) hyperram_pins = self.platform.request("hyperram") else: hyperram_pins = HyperRAMPads() - # broken at the moment - hyperram_pins = None - # set up the SOC soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls, # check microwatt_soc.h for these