From: Luke Kenneth Casson Leighton Date: Thu, 15 Jul 2021 12:51:08 +0000 (+0100) Subject: big intrusive update: merge SVREMAP with SVSTATE, remove SVREMAP X-Git-Tag: xlen-bcd~286 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5eec250d4840e00c13c929df9f3cac0bcc7b5d4;p=openpower-isa.git big intrusive update: merge SVREMAP with SVSTATE, remove SVREMAP this also involved creating an SVP64State class similar to the REMAPP class (now removed). unit tests had to be altered to the new API --- diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 9c4cde86..0556ca34 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -47,12 +47,12 @@ SVRM-Form Pseudo-code: # place into SVREMAP SPR - SVREMAP[10:14] <- SVme - SVREMAP[0:1] <- mi0 - SVREMAP[2:3] <- mi1 - SVREMAP[4:5] <- mi2 - SVREMAP[6:7] <- mo0 - SVREMAP[8:9] <- mo1 + SVSTATE[42:46] <- SVme + SVSTATE[32:33] <- mi0 + SVSTATE[34:35] <- mi1 + SVSTATE[36:37] <- mi2 + SVSTATE[38:39] <- mo0 + SVSTATE[40:41] <- mo1 Special Registers Altered: diff --git a/openpower/isatables/sprs.csv b/openpower/isatables/sprs.csv index 54d0a0cd..624b7fbd 100644 --- a/openpower/isatables/sprs.csv +++ b/openpower/isatables/sprs.csv @@ -65,12 +65,11 @@ Idx,SPR,priv_mtspr,priv_mfspr,len 464,PTCR,hypv,hypv,64 704,SVSTATE,no,no,64 720,PRTBL,yes,yes,64 -721,SVSRR0,yes,yes,32 +721,SVSRR0,yes,yes,64 722,SVSHAPE0,yes,yes,32 723,SVSHAPE1,yes,yes,32 724,SVSHAPE2,yes,yes,32 725,SVSHAPE3,yes,yes,32 -726,SVREMAP,yes,yes,32 727,SVCTX0,yes,yes,64 728,SVCTX1,yes,yes,64 729,SVCTX2,yes,yes,64 diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 79f2e70f..5d5954b3 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -36,7 +36,7 @@ from openpower.decoder.power_svp64 import SVP64RM, decode_extra from openpower.decoder.isa.radixmmu import RADIX from openpower.decoder.isa.mem import Mem, swap_order, MemException from openpower.decoder.isa.svshape import SVSHAPE -from openpower.decoder.isa.svremap import SVREMAP +from openpower.decoder.isa.svstate import SVP64State from openpower.util import log @@ -76,7 +76,6 @@ REG_SORT_ORDER = { "TAR": 0, "MSR": 0, "SVSTATE": 0, - "SVREMAP": 0, "SVSHAPE0": 0, "SVSHAPE1": 0, "SVSHAPE2": 0, @@ -250,19 +249,6 @@ class PC: namespace['NIA'] = self.NIA -# Simple-V: see https://libre-soc.org/openpower/sv -class SVP64State: - def __init__(self, init=0): - self.spr = SelectableInt(init, 64) - # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/ - self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7))) - self.vl = FieldSelectableInt(self.spr, tuple(range(7,14))) - self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21))) - self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28))) - self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30))) - self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32))) - - # SVP64 ReMap field class SVP64RMFields: def __init__(self, init=0): @@ -615,13 +601,6 @@ class ISACaller: val = self.spr[sname].value self.spr[sname] = SVSHAPE(val) self.last_op_svshape = False - # and an SVREMAP - if 'SVREMAP' not in self.spr: - self.spr['SVREMAP'] = SVREMAP(0) - else: - # make sure it's an SVREMAP - val = self.spr['SVREMAP'].value - self.spr['SVREMAP'] = SVREMAP(val) # "raw" memory self.mem = Mem(row_bytes=8, initial_mem=initial_mem) @@ -661,8 +640,7 @@ class ISACaller: 'memassign': self.memassign, 'NIA': self.pc.NIA, 'CIA': self.pc.CIA, - 'SVSTATE': self.svstate.spr, - 'SVREMAP': self.spr['SVREMAP'], + 'SVSTATE': self.svstate, 'SVSHAPE0': self.spr['SVSHAPE0'], 'SVSHAPE1': self.spr['SVSHAPE1'], 'SVSHAPE2': self.spr['SVSHAPE2'], @@ -763,8 +741,8 @@ class ISACaller: self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value # add some SVSTATE convenience variables - vl = self.svstate.vl.asint(msb0=True) - srcstep = self.svstate.srcstep.asint(msb0=True) + vl = self.svstate.vl + srcstep = self.svstate.srcstep self.namespace['VL'] = vl self.namespace['srcstep'] = srcstep @@ -916,7 +894,7 @@ class ISACaller: yield self.dec2.state.msr.eq(self.msr.value) yield self.dec2.state.pc.eq(pc) if self.svstate is not None: - yield self.dec2.state.svstate.eq(self.svstate.spr.value) + yield self.dec2.state.svstate.eq(self.svstate.value) # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set yield Settle() @@ -932,14 +910,14 @@ class ISACaller: self.pc.update_nia(self.is_svp64_mode) yield self.dec2.is_svp64_mode.eq(self.is_svp64_mode) # set SVP64 decode self.namespace['NIA'] = self.pc.NIA - self.namespace['SVSTATE'] = self.svstate.spr + self.namespace['SVSTATE'] = self.svstate if not self.is_svp64_mode: return # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction log ("svp64.rm", bin(pfx.rm.asint(msb0=True))) - log (" svstate.vl", self.svstate.vl.asint(msb0=True)) - log (" svstate.mvl", self.svstate.maxvl.asint(msb0=True)) + log (" svstate.vl", self.svstate.vl) + log (" svstate.mvl", self.svstate.maxvl) sv_rm = pfx.rm.asint(msb0=True) ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True) log(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins))) @@ -1164,7 +1142,7 @@ class ISACaller: srcstep, dststep = self.new_srcstep, self.new_dststep pred_dst_zero = self.pred_dst_zero pred_src_zero = self.pred_src_zero - vl = self.svstate.vl.asint(msb0=True) + vl = self.svstate.vl # VL=0 in SVP64 mode means "do nothing: skip instruction" if self.is_svp64_mode and vl == 0: @@ -1173,11 +1151,9 @@ class ISACaller: self.namespace['NIA']) return - # get the REMAP SPR - SVREMAP = self.spr['SVREMAP'] # for when SVREMAP is active, using pre-arranged schedule. # note: modifying PowerDecoder2 needs to "settle" - remap_en = SVREMAP.men + remap_en = self.svstate.SVme active = self.last_op_svshape and remap_en != 0 yield self.dec2.remap_active.eq(remap_en if active else 0) yield Settle() @@ -1197,11 +1173,16 @@ class ISACaller: log (" skip", shape.skip) # set up the list of steps to remap - steps = [(self.dec2.in1_step, SVREMAP.mi0), # RA - (self.dec2.in2_step, SVREMAP.mi1), # RB - (self.dec2.in3_step, SVREMAP.mi2), # RC - (self.dec2.o_step, SVREMAP.mo0), # RT - (self.dec2.o2_step, SVREMAP.mo1), # EA + mi0 = self.svstate.mi0 + mi1 = self.svstate.mi1 + mi2 = self.svstate.mi2 + mo0 = self.svstate.mo0 + mo1 = self.svstate.mo1 + steps = [(self.dec2.in1_step, mi0), # RA + (self.dec2.in2_step, mi1), # RB + (self.dec2.in3_step, mi2), # RC + (self.dec2.o_step, mo0), # RT + (self.dec2.o2_step, mo1), # EA ] # set up the iterators remaps = [(SVSHAPE0, SVSHAPE0.get_iterator()), @@ -1477,7 +1458,7 @@ class ISACaller: else: log ("SVSTATE_NEXT: post-inc") srcstep, dststep = self.new_srcstep, self.new_dststep - vl = self.svstate.vl.asint(msb0=True) + vl = self.svstate.vl end_src = srcstep == vl-1 end_dst = dststep == vl-1 if not end_src: @@ -1487,8 +1468,8 @@ class ISACaller: self.namespace['SVSTATE'] = self.svstate.spr # set CR0 (if Rc=1) based on end if rc_en: - srcstep = self.svstate.srcstep.asint(msb0=True) - dststep = self.svstate.srcstep.asint(msb0=True) + srcstep = self.svstate.srcstep + dststep = self.svstate.srcstep endtest = 0 if (end_src or end_dst) else 1 results = [SelectableInt(endtest, 64)] self.handle_comparison(results) # CR0 @@ -1522,9 +1503,9 @@ class ISACaller: """check if srcstep/dststep need to skip over masked-out predicate bits """ # get SVSTATE VL (oh and print out some debug stuff) - vl = self.svstate.vl.asint(msb0=True) - srcstep = self.svstate.srcstep.asint(msb0=True) - dststep = self.svstate.dststep.asint(msb0=True) + vl = self.svstate.vl + srcstep = self.svstate.srcstep + dststep = self.svstate.dststep sv_a_nz = yield self.dec2.sv_a_nz fft_mode = yield self.dec2.use_svp64_fft in1 = yield self.dec2.e.read_reg1.data @@ -1588,14 +1569,14 @@ class ISACaller: srcstep, dststep = self.new_srcstep, self.new_dststep # update SVSTATE with new srcstep - self.svstate.srcstep[0:7] = srcstep - self.svstate.dststep[0:7] = dststep - self.namespace['SVSTATE'] = self.svstate.spr - yield self.dec2.state.svstate.eq(self.svstate.spr.value) + self.svstate.srcstep = srcstep + self.svstate.dststep = dststep + self.namespace['SVSTATE'] = self.svstate + yield self.dec2.state.svstate.eq(self.svstate.value) yield Settle() # let decoder update - srcstep = self.svstate.srcstep.asint(msb0=True) - dststep = self.svstate.dststep.asint(msb0=True) - vl = self.svstate.vl.asint(msb0=True) + srcstep = self.svstate.srcstep + dststep = self.svstate.dststep + vl = self.svstate.vl log (" srcstep", srcstep) log (" dststep", dststep) log (" vl", vl) @@ -1614,10 +1595,10 @@ class ISACaller: # check if it is the SVSTATE.src/dest step that needs incrementing # this is our Sub-Program-Counter loop from 0 to VL-1 # XXX twin predication TODO - vl = self.svstate.vl.asint(msb0=True) - mvl = self.svstate.maxvl.asint(msb0=True) - srcstep = self.svstate.srcstep.asint(msb0=True) - dststep = self.svstate.dststep.asint(msb0=True) + vl = self.svstate.vl + mvl = self.svstate.maxvl + srcstep = self.svstate.srcstep + dststep = self.svstate.dststep rm_mode = yield self.dec2.rm_dec.mode reverse_gear = yield self.dec2.rm_dec.reverse_gear sv_ptype = yield self.dec2.dec.op.SV_Ptype @@ -1645,7 +1626,7 @@ class ISACaller: self.svstate.dststep += SelectableInt(1, 7) self.pc.NIA.value = self.pc.CIA.value self.namespace['NIA'] = self.pc.NIA - self.namespace['SVSTATE'] = self.svstate.spr + self.namespace['SVSTATE'] = self.svstate log("end of sub-pc call", self.namespace['CIA'], self.namespace['NIA']) return False # DO NOT allow PC update whilst Sub-PC loop running @@ -1665,10 +1646,10 @@ class ISACaller: self.namespace['SVSTATE']) def svp64_reset_loop(self): - self.svstate.srcstep[0:7] = 0 - self.svstate.dststep[0:7] = 0 + self.svstate.srcstep = 0 + self.svstate.dststep = 0 log (" svstate.srcstep loop end (PC to update)") - self.namespace['SVSTATE'] = self.svstate.spr + self.namespace['SVSTATE'] = self.svstate def update_nia(self): self.pc.update_nia(self.is_svp64_mode) diff --git a/src/openpower/decoder/isa/svremap.py b/src/openpower/decoder/isa/svremap.py deleted file mode 100644 index 7f65267d..00000000 --- a/src/openpower/decoder/isa/svremap.py +++ /dev/null @@ -1,74 +0,0 @@ -from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, - selectconcat) -from openpower.decoder.isa.remapyield import iterate_indices -from openpower.decoder.isa.remap_fft_yield import iterate_butterfly_indices -from openpower.sv.svp64 import SVP64REMAP -import os -from copy import deepcopy -from openpower.util import log - - -class SVREMAP(SelectableInt): - def __init__(self, value): - SelectableInt.__init__(self, value, 32) - offs = 0 - # set up sub-fields from Record layout - self.fsi = {} - l = deepcopy(SVP64REMAP.layout) - l.reverse() - for field, width in l: - end = offs+width - fs = tuple(range(offs, end)) - v = FieldSelectableInt(self, fs) - self.fsi[field] = v - log("SVREMAP setup field", field, offs, end) - offs = end - - @property - def mi0(self): - return self.fsi['mi0'].asint(msb0=True) - - @mi0.setter - def mi0(self, value): - self.fsi['mi0'].eq(mi0) - - @property - def mi1(self): - return self.fsi['mi1'].asint(msb0=True) - - @mi1.setter - def mi1(self, value): - self.fsi['mi1'].eq(mi1) - - @property - def mi2(self): - return self.fsi['mi2'].asint(msb0=True) - - @mi2.setter - def mi2(self, value): - self.fsi['mi2'].eq(mi2) - - @property - def mo0(self): - return self.fsi['mo0'].asint(msb0=True) - - @mo0.setter - def mo0(self, value): - self.fsi['mo0'].eq(mo0) - - @property - def mo1(self): - return self.fsi['mo1'].asint(msb0=True) - - @mo1.setter - def mo1(self, value): - self.fsi['mo1'].eq(mo1) - - @property - def men(self): - return self.fsi['men'].asint(msb0=True) - - @men.setter - def men(self, value): - self.fsi['men'].eq(men) - diff --git a/src/openpower/decoder/isa/svstate.py b/src/openpower/decoder/isa/svstate.py new file mode 100644 index 00000000..6127b25b --- /dev/null +++ b/src/openpower/decoder/isa/svstate.py @@ -0,0 +1,114 @@ +from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, + selectconcat) +from openpower.decoder.isa.remapyield import iterate_indices +from openpower.decoder.isa.remap_fft_yield import iterate_butterfly_indices +from openpower.sv.svstate import SVSTATERec +import os +from copy import deepcopy +from openpower.util import log + + +class SVP64State(SelectableInt): + def __init__(self, value=0): + SelectableInt.__init__(self, value, 64) + offs = 0 + # set up sub-fields from Record layout + self.fsi = {} + l = deepcopy(SVSTATERec.layout) + l.reverse() + for field, width in l: + end = offs+width + fs = tuple(range(offs, end)) + v = FieldSelectableInt(self, fs) + self.fsi[field] = v + log("SVSTATE setup field", field, offs, end) + offs = end + + @property + def maxvl(self): + return self.fsi['maxvl'].asint(msb0=True) + + @maxvl.setter + def maxvl(self, value): + self.fsi['maxvl'].eq(value) + + @property + def vl(self): + return self.fsi['vl'].asint(msb0=True) + + @vl.setter + def vl(self, value): + self.fsi['vl'].eq(value) + + @property + def dststep(self): + return self.fsi['dststep'].asint(msb0=True) + + @dststep.setter + def dststep(self, value): + self.fsi['dststep'].eq(value) + + @property + def srcstep(self): + return self.fsi['srcstep'].asint(msb0=True) + + @srcstep.setter + def srcstep(self, value): + self.fsi['srcstep'].eq(value) + + @property + def subvl(self): + return self.fsi['subvl'].asint(msb0=True) + + @subvl.setter + def subvl(self, value): + self.fsi['subvl'].eq(value) + + @property + def mi0(self): + return self.fsi['mi0'].asint(msb0=True) + + @mi0.setter + def mi0(self, value): + self.fsi['mi0'].eq(value) + + @property + def mi1(self): + return self.fsi['mi1'].asint(msb0=True) + + @mi1.setter + def mi1(self, value): + self.fsi['mi1'].eq(value) + + @property + def mi2(self): + return self.fsi['mi2'].asint(msb0=True) + + @mi2.setter + def mi2(self, value): + self.fsi['mi2'].eq(value) + + @property + def mo0(self): + return self.fsi['mo0'].asint(msb0=True) + + @mo0.setter + def mo0(self, value): + self.fsi['mo0'].eq(value) + + @property + def mo1(self): + return self.fsi['mo1'].asint(msb0=True) + + @mo1.setter + def mo1(self, value): + self.fsi['mo1'].eq(value) + + @property + def SVme(self): + return self.fsi['SVme'].asint(msb0=True) + + @SVme.setter + def SVme(self, value): + self.fsi['SVme'].eq(value) + diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index 369d269f..d86338f2 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -23,7 +23,7 @@ class DecoderTestCase(FHDLTestCase): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) - def test_svstep_1(self): + def test__svstep_1(self): lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode) "setvl 0, 0, 1, 1, 0, 0", # svstep "setvl 0, 0, 1, 1, 0, 0" # svstep @@ -32,27 +32,27 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=4) which is going to get erased by setvl svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.spr.asint())) - print (" vl", bin(sim.svstate.vl.asint(True))) - print (" mvl", bin(sim.svstate.maxvl.asint(True))) - print (" srcstep", bin(sim.svstate.srcstep.asint(True))) - print (" dststep", bin(sim.svstate.dststep.asint(True))) - self.assertEqual(sim.svstate.vl.asint(True), 10) - self.assertEqual(sim.svstate.maxvl.asint(True), 10) - self.assertEqual(sim.svstate.srcstep.asint(True), 2) - self.assertEqual(sim.svstate.dststep.asint(True), 2) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + self.assertEqual(sim.svstate.vl, 10) + self.assertEqual(sim.svstate.maxvl, 10) + self.assertEqual(sim.svstate.srcstep, 2) + self.assertEqual(sim.svstate.dststep, 2) print(" gpr1", sim.gpr(0)) self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) print(" msr", bin(sim.msr.value)) self.assertEqual(sim.msr, SelectableInt(1<<(63-6), 64)) - def test_svstep_2(self): + def test__svstep_2(self): """tests svstep when it reaches VL """ lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", # actual setvl (VF mode) @@ -63,21 +63,21 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.spr.asint())) - print (" vl", bin(sim.svstate.vl.asint(True))) - print (" mvl", bin(sim.svstate.maxvl.asint(True))) - print (" srcstep", bin(sim.svstate.srcstep.asint(True))) - print (" dststep", bin(sim.svstate.dststep.asint(True))) - self.assertEqual(sim.svstate.vl.asint(True), 2) - self.assertEqual(sim.svstate.maxvl.asint(True), 2) - self.assertEqual(sim.svstate.srcstep.asint(True), 0) - self.assertEqual(sim.svstate.dststep.asint(True), 0) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + self.assertEqual(sim.svstate.vl, 2) + self.assertEqual(sim.svstate.maxvl, 2) + self.assertEqual(sim.svstate.srcstep, 0) + self.assertEqual(sim.svstate.dststep, 0) print(" gpr1", sim.gpr(0)) self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) # when end reached, vertical mode is exited @@ -90,7 +90,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(CR0[CRFields.GT], 0) self.assertEqual(CR0[CRFields.SO], 0) - def test_svstep_3(self): + def test__svstep_3(self): """tests svstep when it *doesn't* reach VL """ lst = SVP64Asm(["setvl 0, 0, 3, 1, 1, 1", # actual setvl (VF mode) @@ -101,22 +101,22 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.spr.asint())) - print (" vl", bin(sim.svstate.vl.asint(True))) - print (" mvl", bin(sim.svstate.maxvl.asint(True))) - print (" srcstep", bin(sim.svstate.srcstep.asint(True))) - print (" dststep", bin(sim.svstate.dststep.asint(True))) - self.assertEqual(sim.svstate.vl.asint(True), 3) - self.assertEqual(sim.svstate.maxvl.asint(True), 3) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + self.assertEqual(sim.svstate.vl, 3) + self.assertEqual(sim.svstate.maxvl, 3) # svstep called twice, didn't reach VL, so srcstep/dststep both 2 - self.assertEqual(sim.svstate.srcstep.asint(True), 2) - self.assertEqual(sim.svstate.dststep.asint(True), 2) + self.assertEqual(sim.svstate.srcstep, 2) + self.assertEqual(sim.svstate.dststep, 2) print(" gpr1", sim.gpr(0)) self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) print(" msr", bin(sim.msr.value)) @@ -129,7 +129,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(CR0[CRFields.SO], 0) - def test_setvl_1(self): + def test__setvl_1(self): """straight setvl, testing if VL and MVL are over-ridden """ lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1", @@ -138,22 +138,22 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2), want to see if these get changed svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.spr.asint())) - print (" vl", bin(sim.svstate.vl.asint(True))) - print (" mvl", bin(sim.svstate.maxvl.asint(True))) - self.assertEqual(sim.svstate.vl.asint(True), 10) - self.assertEqual(sim.svstate.maxvl.asint(True), 10) - self.assertEqual(sim.svstate.maxvl.asint(True), 10) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + self.assertEqual(sim.svstate.vl, 10) + self.assertEqual(sim.svstate.maxvl, 10) + self.assertEqual(sim.svstate.maxvl, 10) print(" gpr1", sim.gpr(1)) self.assertEqual(sim.gpr(1), SelectableInt(10, 64)) - def test_sv_add(self): + def test__sv_add(self): """sets VL=2 then adds: * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 @@ -181,7 +181,7 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs) self._check_regs(sim, expected_regs) - def test_svstep_add_1(self): + def test__svstep_add_1(self): """tests svstep with an add, when it reaches VL lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', @@ -209,9 +209,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # initial values in GPR regfile initial_regs = [0] * 32 @@ -228,15 +228,15 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.spr.asint())) - print (" vl", bin(sim.svstate.vl.asint(True))) - print (" mvl", bin(sim.svstate.maxvl.asint(True))) - print (" srcstep", bin(sim.svstate.srcstep.asint(True))) - print (" dststep", bin(sim.svstate.dststep.asint(True))) - self.assertEqual(sim.svstate.vl.asint(True), 2) - self.assertEqual(sim.svstate.maxvl.asint(True), 2) - self.assertEqual(sim.svstate.srcstep.asint(True), 0) - self.assertEqual(sim.svstate.dststep.asint(True), 0) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + self.assertEqual(sim.svstate.vl, 2) + self.assertEqual(sim.svstate.maxvl, 2) + self.assertEqual(sim.svstate.srcstep, 0) + self.assertEqual(sim.svstate.dststep, 0) # when end reached, vertical mode is exited print(" msr", bin(sim.msr.value)) self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64)) @@ -250,7 +250,7 @@ class DecoderTestCase(FHDLTestCase): # check registers as expected self._check_regs(sim, expected_regs) - def test_svstep_add_2(self): + def test__svstep_add_2(self): """tests svstep with a branch. lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', @@ -287,9 +287,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # initial values in GPR regfile initial_regs = [0] * 32 @@ -306,15 +306,15 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.spr.asint())) - print (" vl", bin(sim.svstate.vl.asint(True))) - print (" mvl", bin(sim.svstate.maxvl.asint(True))) - print (" srcstep", bin(sim.svstate.srcstep.asint(True))) - print (" dststep", bin(sim.svstate.dststep.asint(True))) - self.assertEqual(sim.svstate.vl.asint(True), 2) - self.assertEqual(sim.svstate.maxvl.asint(True), 2) - self.assertEqual(sim.svstate.srcstep.asint(True), 0) - self.assertEqual(sim.svstate.dststep.asint(True), 0) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + self.assertEqual(sim.svstate.vl, 2) + self.assertEqual(sim.svstate.maxvl, 2) + self.assertEqual(sim.svstate.srcstep, 0) + self.assertEqual(sim.svstate.dststep, 0) # when end reached, vertical mode is exited print(" msr", bin(sim.msr.value)) self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64)) @@ -337,15 +337,15 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program) - svremap = sim.spr('SVREMAP') + svremap = sim.svstate print ("SVREMAP after", bin(svremap.value)) - print (" men", bin(svremap.men)) + print (" men", bin(svremap.SVme)) print (" mi0", bin(svremap.mi0)) print (" mi1", bin(svremap.mi1)) print (" mi2", bin(svremap.mi2)) print (" mo0", bin(svremap.mo0)) print (" mo1", bin(svremap.mo1)) - self.assertEqual(svremap.men, 11) + self.assertEqual(svremap.SVme, 11) self.assertEqual(svremap.mi0, 0) self.assertEqual(svremap.mi1, 1) self.assertEqual(svremap.mi2, 2) diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py index 5f92e07c..191d0ce2 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fft.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py @@ -244,9 +244,9 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (calculated VL) svstate = SVP64State() - svstate.vl[0:7] = VL # VL - svstate.maxvl[0:7] = VL # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = VL # VL + svstate.maxvl = VL # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -348,9 +348,9 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (calculated VL) svstate = SVP64State() - svstate.vl[0:7] = VL # VL - svstate.maxvl[0:7] = VL # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = VL # VL + svstate.maxvl = VL # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -421,9 +421,9 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -466,9 +466,9 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -573,9 +573,9 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (calculated VL) svstate = SVP64State() - svstate.vl[0:7] = VL # VL - svstate.maxvl[0:7] = VL # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = VL # VL + svstate.maxvl = VL # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -643,9 +643,9 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py index 96b0199d..51782281 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fp.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py @@ -32,9 +32,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # memory addresses 0x0000 and 0x0008 initial_mem = {0x0000: (0x42013333, 8), # 32.3 @@ -99,9 +99,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # memory addresses 0x0000 and 0x0008 initial_mem = {0x0000: (0x42013333, 8), # 32.3 @@ -147,9 +147,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -179,9 +179,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py index c30e41be..76094678 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py @@ -43,9 +43,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x0404 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) # r1 = r1 + r5 + r6 @@ -80,9 +80,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[4] = 0x4 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) for i in range(3): @@ -117,9 +117,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[4] = 0x1 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) for i in range(3): @@ -158,9 +158,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -190,9 +190,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 99ca74df..accbcd68 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -76,15 +76,8 @@ class DecoderTestCase(FHDLTestCase): #print ("FFT", i, "in", a, b, "coeff", c, "mul", # mul, "res", t, u) - # SVSTATE (in this case, VL=12, to cover all of matrix) - svstate = SVP64State() - svstate.vl[0:7] = 12 # VL - svstate.maxvl[0:7] = 12 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, svstate=svstate, - initial_fprs=fprs) + sim = self.run_tst_program(program, initial_fprs=fprs) print ("spr svshape0", sim.spr['SVSHAPE0']) print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index d96ed2cd..c34094ee 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -32,9 +32,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) @@ -76,9 +76,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[10] = 0x90 # this gets skipped # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0x0 # dest r3 is 0b10: skip @@ -104,9 +104,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[10] = 0x90 # this gets read but the output gets zero'd # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store @@ -142,9 +142,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[1] = 0xbeef @@ -172,9 +172,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[1] = 0xbeef @@ -209,9 +209,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[11] = 0x92 # source r3 is 0b101 so this will be used # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0xffff_ffff_ffff_ff90 # (from r9) @@ -243,9 +243,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[11] = 0x92 # the VL loop runs out before we can use it # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0xffff_ffff_ffff_ff90 # 1st bit of r3 is 1 @@ -276,9 +276,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[11] = 0x92 # VL loop runs out before we can use it # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0x0 # dest ~r3 is 0b010: skip @@ -318,12 +318,12 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL # set src/dest step on the middle of the loop - svstate.srcstep[0:7] = 1 - svstate.dststep[0:7] = 2 - print("SVSTATE", bin(svstate.spr.asint())) + svstate.srcstep = 1 + svstate.dststep = 2 + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0x0 # skip @@ -356,9 +356,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[11] = 0x92 # 3rd bit of r30 is 1 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0x0 # skip @@ -390,9 +390,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[11] = 0x92 # r3 is 2, so this will be used # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0x0 # skip @@ -436,12 +436,12 @@ class DecoderTestCase(FHDLTestCase): cr.crl[7][CRFields.LT] = 1 # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL # set src/dest step on the middle of the loop - svstate.srcstep[0:7] = 1 - svstate.dststep[0:7] = 2 - print("SVSTATE", bin(svstate.spr.asint())) + svstate.srcstep = 1 + svstate.dststep = 2 + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0x0 # skip diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index 565480cf..dafcc2cb 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -49,11 +49,11 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE (in this case, VL=3, and src/dststep set ALREADY to 1) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - svstate.srcstep[0:7] = 1 # srcstep - svstate.dststep[0:7] = 1 # srcstep - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + svstate.srcstep = 1 # srcstep + svstate.dststep = 1 # srcstep + print ("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -108,9 +108,9 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) # initial values in GPR regfile initial_regs = [0] * 32 @@ -128,15 +128,15 @@ class SVSTATETestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.spr.asint())) - print (" vl", bin(sim.svstate.vl.asint(True))) - print (" mvl", bin(sim.svstate.maxvl.asint(True))) - print (" srcstep", bin(sim.svstate.srcstep.asint(True))) - print (" dststep", bin(sim.svstate.dststep.asint(True))) - self.assertEqual(sim.svstate.vl.asint(True), 2) - self.assertEqual(sim.svstate.maxvl.asint(True), 2) - self.assertEqual(sim.svstate.srcstep.asint(True), 0) - self.assertEqual(sim.svstate.dststep.asint(True), 0) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + self.assertEqual(sim.svstate.vl, 2) + self.assertEqual(sim.svstate.maxvl, 2) + self.assertEqual(sim.svstate.srcstep, 0) + self.assertEqual(sim.svstate.dststep, 0) # when end reached, vertical mode is exited print(" msr", bin(sim.msr.value)) # should be zero self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64)) diff --git a/src/openpower/sv/svp64.py b/src/openpower/sv/svp64.py index b892abbe..a70ae4e9 100644 --- a/src/openpower/sv/svp64.py +++ b/src/openpower/sv/svp64.py @@ -107,9 +107,9 @@ class SVP64REMAP(Record): ("mi0" , 2), ] - """SVP64 REMAP Record. + """SVP64 REMAP Record, for Context Propagation - https://libre-soc.org/openpower/sv/remap/ + https://libre-soc.org/openpower/sv/propagation/ | Field Name | Field bits | Description | |------------|------------|----------------------------------------| diff --git a/src/openpower/sv/svstate.py b/src/openpower/sv/svstate.py index 9d593e18..281c8aad 100644 --- a/src/openpower/sv/svstate.py +++ b/src/openpower/sv/svstate.py @@ -13,20 +13,39 @@ https://libre-soc.org/openpower/sv/sprs/ | 21:27 | dststep | for dststep = 0..VL-1 | | 28:29 | subvl | Sub-vector length | | 30:31 | svstep | for svstep = 0..SUBVL-1 | +| 32:33 | mi0 | REMAP RA SVSHAPE0-3 | +| 34:35 | mi1 | REMAP RB SVSHAPE0-3 | +| 36:37 | mi2 | REMAP RC SVSHAPE0-3 | +| 38:39 | mo0 | REMAP RT SVSHAPE0-3 | +| 40:41 | mo1 | REMAP EA SVSHAPE0-3 | +| 42:46 | SVme | REMAP enable (RA-RT) | +| 47:61 | rsvd | reserved | +| 62 | RMpst | REMAP persistence | +| 63 | vfirst | Vertical First mode | """ -from nmutil.iocontrol import RecordObject -from nmigen import Signal +from nmigen import Signal, Record # In nMigen, Record order is from LSB to MSB -class SVSTATERec(RecordObject): +# but Power ISA specs are all MSB to LSB (MSB0). +class SVSTATERec(Record): + layout = [("vfirst", 1), + ("RMpst", 1), + ("rsvd", 15), + ("SVme", 5), + ("mo1", 2), + ("mo0", 2), + ("mi2", 2), + ("mi1", 2), + ("mi0", 2), + ("svstep", 2), + ("subvl", 2), + ("dststep", 7), + ("srcstep", 7), + ("vl", 7), + ("maxvl", 7), + ] + def __init__(self, name=None): - super().__init__(name=name) - self.rsvd = Signal(32) # TODO - self.svstep = Signal(2) - self.subvl = Signal(2) - self.dststep = Signal(7) - self.srcstep = Signal(7) - self.vl = Signal(7) - self.maxvl = Signal(7) + super().__init__(name=name, layout=SVSTATERec.layout) diff --git a/src/openpower/test/alu/svp64_cases.py b/src/openpower/test/alu/svp64_cases.py index 697ee2b8..cb75f205 100644 --- a/src/openpower/test/alu/svp64_cases.py +++ b/src/openpower/test/alu/svp64_cases.py @@ -26,9 +26,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -49,9 +49,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[5] = 0x4321 svstate = SVP64State() # SVSTATE (in this case, VL=1, so everything works as in v3.0B) - svstate.vl[0:7] = 1 # VL - svstate.maxvl[0:7] = 1 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 1 # VL + svstate.maxvl = 1 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -78,9 +78,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[10] = 0x1230 svstate = SVP64State() # SVSTATE (in this case, VL=1, so everything works as in v3.0B) - svstate.vl[0:7] = 1 # VL - svstate.maxvl[0:7] = 1 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 1 # VL + svstate.maxvl = 1 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -105,9 +105,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -136,9 +136,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[10] = 0x1230 svstate = SVP64State() # SVSTATE (in this case, VL=0, so vector instructions are skipped) - svstate.vl[0:7] = 0 # VL - svstate.maxvl[0:7] = 0 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 0 # VL + svstate.maxvl = 0 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -175,9 +175,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[7] = 0x1230 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -201,9 +201,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -226,9 +226,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -272,9 +272,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[8] = 0x8051 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -320,9 +320,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[8] = 0x8051 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -351,9 +351,9 @@ class SVP64ALUTestCase(TestAccumulatorBase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # set up CR predicate - CR4.eq=1 and CR5.eq=0 cr = 0b0010 << ((7-4)*4) # CR4.eq (we hope) diff --git a/src/openpower/test/logical/svp64_cases.py b/src/openpower/test/logical/svp64_cases.py index 88c0de5b..0d84f66b 100644 --- a/src/openpower/test/logical/svp64_cases.py +++ b/src/openpower/test/logical/svp64_cases.py @@ -48,9 +48,9 @@ class SVP64LogicalTestCase(TestAccumulatorBase): initial_regs[10] = 0x90 # this gets skipped # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -85,9 +85,9 @@ class SVP64LogicalTestCase(TestAccumulatorBase): initial_regs[11] = 0x92 # source r3 is 0b101 so this will be used # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -122,9 +122,9 @@ class SVP64LogicalTestCase(TestAccumulatorBase): initial_regs[11] = 0x92 # the VL loop runs out before we can use it # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -158,9 +158,9 @@ class SVP64LogicalTestCase(TestAccumulatorBase): initial_regs[11] = 0x92 # VL loop runs out before we can use it # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -210,12 +210,12 @@ class SVP64LogicalTestCase(TestAccumulatorBase): # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL # set src/dest step on the middle of the loop - svstate.srcstep[0:7] = 1 - svstate.dststep[0:7] = 2 - print("SVSTATE", bin(svstate.spr.asint())) + svstate.srcstep = 1 + svstate.dststep = 2 + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -254,9 +254,9 @@ class SVP64LogicalTestCase(TestAccumulatorBase): initial_regs[11] = 0x92 # 3rd bit of r30 is 1 # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -291,9 +291,9 @@ class SVP64LogicalTestCase(TestAccumulatorBase): initial_regs[11] = 0x92 # r3 is 2, so this will be used # SVSTATE (in this case, VL=3) svstate = SVP64State() - svstate.vl[0:7] = 3 # VL - svstate.maxvl[0:7] = 3 # MAXVL - print("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) @@ -351,12 +351,12 @@ class SVP64LogicalTestCase(TestAccumulatorBase): cr.crl[7][CRFields.LT] = 1 # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl[0:7] = 4 # VL - svstate.maxvl[0:7] = 4 # MAXVL + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL # set src/dest step on the middle of the loop - svstate.srcstep[0:7] = 1 - svstate.dststep[0:7] = 2 - print("SVSTATE", bin(svstate.spr.asint())) + svstate.srcstep = 1 + svstate.dststep = 2 + print("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate, initial_cr=cr.cr.asint()) @@ -382,9 +382,9 @@ class SVP64LogicalTestCase(TestAccumulatorBase): initial_regs[10] = 0x90 # this gets read but the output gets zero'd # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate)