From: Stefan Biereigel <stefan@biereigel.de>
Date: Mon, 27 May 2019 16:10:39 +0000 (+0200)
Subject: remove port direction workaround from test case
X-Git-Tag: yosys-0.9~102^2~2^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839;p=yosys.git

remove port direction workaround from test case
---

diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v
index 824f89683..d1dca6269 100644
--- a/tests/various/wandwor.v
+++ b/tests/various/wandwor.v
@@ -17,7 +17,6 @@ module c;
 
 
     wand E;
-    wire E_wire = E;
     
     genvar i;
     for (i = 0; i < 3; i = i + 1)
@@ -27,7 +26,7 @@ module c;
         );
         
         b b_inst (
-            .D(E_wire)
+            .D(E)
         );
     end