From: Luke Kenneth Casson Leighton Date: Thu, 2 Jul 2020 22:54:53 +0000 (+0000) Subject: name ALUs so as to not have to change cells.lst X-Git-Tag: partial-core-ls180-gdsii~108 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c601f60f2296fcdeca23a26cc723de24c4c85f0f;p=soclayout.git name ALUs so as to not have to change cells.lst --- diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il index ea053fd..6c7e903 100644 --- a/experiments9/non_generated/test_issuer.il +++ b/experiments9/non_generated/test_issuer.il @@ -40651,7 +40651,7 @@ module \pdecode2 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.p" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i @@ -40679,7 +40679,7 @@ module \p end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.n" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o @@ -40707,7 +40707,7 @@ module \n end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.p" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.p" module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i @@ -40735,7 +40735,7 @@ module \p$1 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.n" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.n" module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o @@ -40763,7 +40763,7 @@ module \n$2 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.input" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.input" module \input attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid @@ -41154,7 +41154,7 @@ module \input end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.main" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.main" module \main attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid @@ -42256,7 +42256,7 @@ module \main end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.output" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.output" module \output attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid @@ -42917,7 +42917,7 @@ module \output end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe" module \pipe attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst @@ -45105,8 +45105,8 @@ module \pipe connect \xer_so_ok$119 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu" -module \alu +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" +module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -45956,19 +45956,19 @@ module \src_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \r_src + wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -45976,9 +45976,9 @@ module \src_l connect \A \r_src connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -45989,9 +45989,9 @@ module \src_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -46015,9 +46015,9 @@ module \src_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -46025,9 +46025,9 @@ module \src_l connect \A \r_src connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -46038,9 +46038,9 @@ module \src_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -46056,11 +46056,11 @@ module \src_l assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -46073,11 +46073,11 @@ module \src_l assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -46101,19 +46101,19 @@ module \opc_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_opc + wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46121,9 +46121,9 @@ module \opc_l connect \A \r_opc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46134,9 +46134,9 @@ module \opc_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46160,9 +46160,9 @@ module \opc_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46170,9 +46170,9 @@ module \opc_l connect \A \r_opc connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46183,9 +46183,9 @@ module \opc_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46201,11 +46201,11 @@ module \opc_l assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46218,11 +46218,11 @@ module \opc_l assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46246,19 +46246,19 @@ module \req_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46266,9 +46266,9 @@ module \req_l connect \A \r_req connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46279,9 +46279,9 @@ module \req_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46305,9 +46305,9 @@ module \req_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46315,9 +46315,9 @@ module \req_l connect \A \r_req connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46328,9 +46328,9 @@ module \req_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46346,11 +46346,11 @@ module \req_l assign \q_req $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46363,11 +46363,11 @@ module \req_l assign \qn_req $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 5 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -46391,17 +46391,17 @@ module \rst_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46409,9 +46409,9 @@ module \rst_l connect \A \r_rst connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46422,9 +46422,9 @@ module \rst_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46448,11 +46448,11 @@ module \rst_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46460,9 +46460,9 @@ module \rst_l connect \A \r_rst connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46473,9 +46473,9 @@ module \rst_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46491,11 +46491,11 @@ module \rst_l assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46508,11 +46508,11 @@ module \rst_l assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46536,19 +46536,19 @@ module \rok_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46556,9 +46556,9 @@ module \rok_l connect \A \r_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46569,9 +46569,9 @@ module \rok_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46595,9 +46595,9 @@ module \rok_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46605,9 +46605,9 @@ module \rok_l connect \A \r_rdok connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46618,9 +46618,9 @@ module \rok_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46636,11 +46636,11 @@ module \rok_l assign \q_rdok $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46653,11 +46653,11 @@ module \rok_l assign \qn_rdok $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46681,19 +46681,19 @@ module \alui_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46701,9 +46701,9 @@ module \alui_l connect \A \r_alui connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46714,9 +46714,9 @@ module \alui_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46740,9 +46740,9 @@ module \alui_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46750,9 +46750,9 @@ module \alui_l connect \A \r_alui connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46763,9 +46763,9 @@ module \alui_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46781,11 +46781,11 @@ module \alui_l assign \q_alui $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46798,11 +46798,11 @@ module \alui_l assign \qn_alui $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46826,19 +46826,19 @@ module \alu_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46846,9 +46846,9 @@ module \alu_l connect \A \r_alu connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46859,9 +46859,9 @@ module \alu_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46885,9 +46885,9 @@ module \alu_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46895,9 +46895,9 @@ module \alu_l connect \A \r_alu connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46908,9 +46908,9 @@ module \alu_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46926,11 +46926,11 @@ module \alu_l assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -46943,11 +46943,11 @@ module \alu_l assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47155,9 +47155,9 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" wire width 64 output 49 \dest1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" - wire width 1 \alu_n_valid_o + wire width 1 \alu_alu0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" - wire width 1 \alu_n_ready_i + wire width 1 \alu_alu0_n_ready_i attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -47231,7 +47231,7 @@ module \alu0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 7 \alu_op__insn_type + wire width 7 \alu_alu0_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -47244,68 +47244,68 @@ module \alu0 attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \alu_op__fn_unit + wire width 10 \alu_alu0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 64 \alu_op__imm_data__imm + wire width 64 \alu_alu0_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__imm_data__imm_ok + wire width 1 \alu_alu0_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__lk + wire width 1 \alu_alu0_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__rc__rc + wire width 1 \alu_alu0_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__rc__rc_ok + wire width 1 \alu_alu0_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__oe__oe + wire width 1 \alu_alu0_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__oe__oe_ok + wire width 1 \alu_alu0_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__invert_a + wire width 1 \alu_alu0_op__invert_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__zero_a + wire width 1 \alu_alu0_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__invert_out + wire width 1 \alu_alu0_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 3 \alu_op__write_cr__data + wire width 3 \alu_alu0_op__write_cr__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__write_cr__ok + wire width 1 \alu_alu0_op__write_cr__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 2 \alu_op__input_carry + wire width 2 \alu_alu0_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__output_carry + wire width 1 \alu_alu0_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__input_cr + wire width 1 \alu_alu0_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__output_cr + wire width 1 \alu_alu0_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__is_32bit + wire width 1 \alu_alu0_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__is_signed + wire width 1 \alu_alu0_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 4 \alu_op__data_len + wire width 4 \alu_alu0_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 32 \alu_op__insn + wire width 32 \alu_alu0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__byte_reverse + wire width 1 \alu_alu0_op__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 \alu_op__sign_extend + wire width 1 \alu_alu0_op__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_ra + wire width 64 \alu_alu0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_rb + wire width 64 \alu_alu0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 1 \alu_xer_so + wire width 1 \alu_alu0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 2 \alu_xer_ca + wire width 2 \alu_alu0_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" - wire width 1 \alu_p_valid_i + wire width 1 \alu_alu0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" - wire width 1 \alu_p_ready_o - cell \alu \alu + wire width 1 \alu_alu0_p_ready_o + cell \alu_alu0 \alu_alu0 connect \rst \rst connect \clk \clk connect \o_ok \o_ok @@ -47318,48 +47318,48 @@ module \alu0 connect \xer_ov \xer_ov connect \xer_so_ok \xer_so_ok connect \xer_so \xer_so - connect \n_valid_o \alu_n_valid_o - connect \n_ready_i \alu_n_ready_i - connect \op__insn_type \alu_op__insn_type - connect \op__fn_unit \alu_op__fn_unit - connect \op__imm_data__imm \alu_op__imm_data__imm - connect \op__imm_data__imm_ok \alu_op__imm_data__imm_ok - connect \op__lk \alu_op__lk - connect \op__rc__rc \alu_op__rc__rc - connect \op__rc__rc_ok \alu_op__rc__rc_ok - connect \op__oe__oe \alu_op__oe__oe - connect \op__oe__oe_ok \alu_op__oe__oe_ok - connect \op__invert_a \alu_op__invert_a - connect \op__zero_a \alu_op__zero_a - connect \op__invert_out \alu_op__invert_out - connect \op__write_cr__data \alu_op__write_cr__data - connect \op__write_cr__ok \alu_op__write_cr__ok - connect \op__input_carry \alu_op__input_carry - connect \op__output_carry \alu_op__output_carry - connect \op__input_cr \alu_op__input_cr - connect \op__output_cr \alu_op__output_cr - connect \op__is_32bit \alu_op__is_32bit - connect \op__is_signed \alu_op__is_signed - connect \op__data_len \alu_op__data_len - connect \op__insn \alu_op__insn - connect \op__byte_reverse \alu_op__byte_reverse - connect \op__sign_extend \alu_op__sign_extend - connect \ra \alu_ra - connect \rb \alu_rb - connect \xer_so$1 \alu_xer_so - connect \xer_ca$2 \alu_xer_ca - connect \p_valid_i \alu_p_valid_i - connect \p_ready_o \alu_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + connect \n_valid_o \alu_alu0_n_valid_o + connect \n_ready_i \alu_alu0_n_ready_i + connect \op__insn_type \alu_alu0_op__insn_type + connect \op__fn_unit \alu_alu0_op__fn_unit + connect \op__imm_data__imm \alu_alu0_op__imm_data__imm + connect \op__imm_data__imm_ok \alu_alu0_op__imm_data__imm_ok + connect \op__lk \alu_alu0_op__lk + connect \op__rc__rc \alu_alu0_op__rc__rc + connect \op__rc__rc_ok \alu_alu0_op__rc__rc_ok + connect \op__oe__oe \alu_alu0_op__oe__oe + connect \op__oe__oe_ok \alu_alu0_op__oe__oe_ok + connect \op__invert_a \alu_alu0_op__invert_a + connect \op__zero_a \alu_alu0_op__zero_a + connect \op__invert_out \alu_alu0_op__invert_out + connect \op__write_cr__data \alu_alu0_op__write_cr__data + connect \op__write_cr__ok \alu_alu0_op__write_cr__ok + connect \op__input_carry \alu_alu0_op__input_carry + connect \op__output_carry \alu_alu0_op__output_carry + connect \op__input_cr \alu_alu0_op__input_cr + connect \op__output_cr \alu_alu0_op__output_cr + connect \op__is_32bit \alu_alu0_op__is_32bit + connect \op__is_signed \alu_alu0_op__is_signed + connect \op__data_len \alu_alu0_op__data_len + connect \op__insn \alu_alu0_op__insn + connect \op__byte_reverse \alu_alu0_op__byte_reverse + connect \op__sign_extend \alu_alu0_op__sign_extend + connect \ra \alu_alu0_ra + connect \rb \alu_alu0_rb + connect \xer_so$1 \alu_alu0_xer_so + connect \xer_ca$2 \alu_alu0_xer_ca + connect \p_valid_i \alu_alu0_p_valid_i + connect \p_ready_o \alu_alu0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 4 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src cell \src_l \src_l connect \rst \rst @@ -47368,15 +47368,15 @@ module \alu0 connect \r_src \src_l_r_src connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc cell \opc_l \opc_l connect \rst \rst @@ -47385,11 +47385,11 @@ module \alu0 connect \r_opc \opc_l_r_opc connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 5 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 5 \req_l_r_req cell \req_l \req_l connect \rst \rst @@ -47398,9 +47398,9 @@ module \alu0 connect \s_req \req_l_s_req connect \r_req \req_l_r_req end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst cell \rst_l \rst_l connect \rst \rst @@ -47408,13 +47408,13 @@ module \alu0 connect \s_rst \rst_l_s_rst connect \r_rst \rst_l_r_rst end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next cell \rok_l \rok_l connect \rst \rst @@ -47423,13 +47423,13 @@ module \alu0 connect \s_rdok \rok_l_s_rdok connect \r_rdok \rok_l_r_rdok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui cell \alui_l \alui_l connect \rst \rst @@ -47438,13 +47438,13 @@ module \alu0 connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu cell \alu_l \alu_l connect \rst \rst @@ -47453,11 +47453,11 @@ module \alu0 connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177" - wire width 1 \all_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47468,11 +47468,11 @@ module \alu0 connect \B \rok_l_q_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 4 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -47480,9 +47480,9 @@ module \alu0 connect \A \rd__rel connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 4 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $or $7 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -47493,7 +47493,7 @@ module \alu0 connect \B \rd__go connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $reduce_and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -47501,9 +47501,9 @@ module \alu0 connect \A $6 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47519,9 +47519,9 @@ module \alu0 assign \all_rd $9 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -47531,11 +47531,11 @@ module \alu0 sync posedge \clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184" wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $not $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47543,9 +47543,9 @@ module \alu0 connect \A \all_rd_dly connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $and $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47561,16 +47561,16 @@ module \alu0 assign \all_rd_pulse $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 \alu_done process $group_3 assign \alu_done 1'0 - assign \alu_done \alu_n_valid_o + assign \alu_done \alu_alu0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly$next process $group_4 assign \alu_done_dly$next \alu_done_dly @@ -47580,11 +47580,11 @@ module \alu0 sync posedge \clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $not $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47592,9 +47592,9 @@ module \alu0 connect \A \alu_done_dly connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $and $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47610,20 +47610,20 @@ module \alu0 assign \alu_pulse $17 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire width 5 \alu_pulsem process $group_6 assign \alu_pulsem 5'00000 assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" wire width 5 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47649,15 +47649,15 @@ module \alu0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire width 1 \done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 5 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" wire width 5 \wrmask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47665,9 +47665,9 @@ module \alu0 connect \A \wrmask connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 5 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47678,7 +47678,7 @@ module \alu0 connect \B $23 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $reduce_bool $27 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47686,7 +47686,7 @@ module \alu0 connect \A $25 connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47694,9 +47694,9 @@ module \alu0 connect \A $22 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47712,11 +47712,11 @@ module \alu0 assign \done_o $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47724,9 +47724,9 @@ module \alu0 connect \A \wr__go connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $34 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47734,9 +47734,9 @@ module \alu0 connect \A \prev_wr_go connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47752,21 +47752,21 @@ module \alu0 assign \wr_any $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_ready_i + connect \A \alu_alu0_n_ready_i connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47777,9 +47777,9 @@ module \alu0 connect \B $37 connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 5 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47790,9 +47790,9 @@ module \alu0 connect \B \wrmask connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47803,9 +47803,9 @@ module \alu0 connect \B 1'0 connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47816,9 +47816,9 @@ module \alu0 connect \B $43 connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47829,9 +47829,9 @@ module \alu0 connect \B 1'0 connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47839,12 +47839,12 @@ module \alu0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $47 - connect \B \alu_n_ready_i + connect \B \alu_alu0_n_ready_i connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47852,12 +47852,12 @@ module \alu0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_n_valid_o + connect \B \alu_alu0_n_valid_o connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47871,19 +47871,19 @@ module \alu0 process $group_10 assign \req_done 1'0 assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" cell $or $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47899,11 +47899,11 @@ module \alu0 assign \reset $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" cell $or $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -47919,11 +47919,11 @@ module \alu0 assign \rst_r $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 5 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" cell $or $60 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -47939,11 +47939,11 @@ module \alu0 assign \reset_w $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 4 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" cell $or $62 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -47964,16 +47964,16 @@ module \alu0 assign \rok_l_s_rdok \issue_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_alu0_n_valid_o connect \B \busy_o connect \Y $63 end @@ -48052,9 +48052,9 @@ module \alu0 sync posedge \clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" wire width 5 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -48070,9 +48070,9 @@ module \alu0 assign \req_l_s_req $65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" wire width 5 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" cell $or $68 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -48088,199 +48088,6 @@ module \alu0 assign \req_l_r_req $67 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__lk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__lk$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_out - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_out$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 3 \oper_l__write_cr__data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 3 \oper_l__write_cr__data$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr__ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr__ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \oper_l__input_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \oper_l__input_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__input_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__input_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__byte_reverse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__byte_reverse$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__sign_extend - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__sign_extend$next - process $group_25 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__lk$next \oper_l__lk - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__invert_a$next \oper_l__invert_a - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__invert_out$next \oper_l__invert_out - assign \oper_l__write_cr__data$next \oper_l__write_cr__data - assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__input_cr$next \oper_l__input_cr - assign \oper_l__output_cr$next \oper_l__output_cr - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len - assign \oper_l__insn$next \oper_l__insn - assign \oper_l__byte_reverse$next \oper_l__byte_reverse - assign \oper_l__sign_extend$next \oper_l__sign_extend - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - assign \oper_l__write_cr__data$next 3'000 - assign \oper_l__write_cr__ok$next 1'0 - assign \oper_l__insn$next 32'00000000000000000000000000000000 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__lk 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__invert_a 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__invert_out 1'0 - update \oper_l__write_cr__data 3'000 - update \oper_l__write_cr__ok 1'0 - update \oper_l__input_carry 2'00 - update \oper_l__output_carry 1'0 - update \oper_l__input_cr 1'0 - update \oper_l__output_cr 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 - update \oper_l__insn 32'00000000000000000000000000000000 - update \oper_l__byte_reverse 1'0 - update \oper_l__sign_extend 1'0 - sync posedge \clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__lk \oper_l__lk$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__invert_a \oper_l__invert_a$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__invert_out \oper_l__invert_out$next - update \oper_l__write_cr__data \oper_l__write_cr__data$next - update \oper_l__write_cr__ok \oper_l__write_cr__ok$next - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__input_cr \oper_l__input_cr$next - update \oper_l__output_cr \oper_l__output_cr$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next - update \oper_l__insn \oper_l__insn$next - update \oper_l__byte_reverse \oper_l__byte_reverse$next - update \oper_l__sign_extend \oper_l__sign_extend$next - end attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -48416,7 +48223,113 @@ module \alu0 wire width 1 \oper_r__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 \oper_r__sign_extend - process $group_49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_out + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_out$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__input_cr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__input_cr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_cr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_cr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__byte_reverse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__sign_extend + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__sign_extend$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 139 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $70 + parameter \WIDTH 139 + connect \A { \oper_l__sign_extend \oper_l__byte_reverse \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + connect \S \issue_i + connect \Y $69 + end + process $group_25 assign \oper_r__insn_type 7'0000000 assign \oper_r__fn_unit 10'0000000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -48441,45 +48354,160 @@ module \alu0 assign \oper_r__insn 32'00000000000000000000000000000000 assign \oper_r__byte_reverse 1'0 assign \oper_r__sign_extend 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69 + sync init + end + process $group_49 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm + assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok + assign \oper_l__lk$next \oper_l__lk + assign \oper_l__rc__rc$next \oper_l__rc__rc + assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok + assign \oper_l__oe__oe$next \oper_l__oe__oe + assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok + assign \oper_l__invert_a$next \oper_l__invert_a + assign \oper_l__zero_a$next \oper_l__zero_a + assign \oper_l__invert_out$next \oper_l__invert_out + assign \oper_l__write_cr__data$next \oper_l__write_cr__data + assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok + assign \oper_l__input_carry$next \oper_l__input_carry + assign \oper_l__output_carry$next \oper_l__output_carry + assign \oper_l__input_cr$next \oper_l__input_cr + assign \oper_l__output_cr$next \oper_l__output_cr + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__is_signed$next \oper_l__is_signed + assign \oper_l__data_len$next \oper_l__data_len + assign \oper_l__insn$next \oper_l__insn + assign \oper_l__byte_reverse$next \oper_l__byte_reverse + assign \oper_l__sign_extend$next \oper_l__sign_extend + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__sign_extend \oper_l__byte_reverse \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + assign { \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_l__imm_data__imm_ok$next 1'0 + assign \oper_l__rc__rc$next 1'0 + assign \oper_l__rc__rc_ok$next 1'0 + assign \oper_l__oe__oe$next 1'0 + assign \oper_l__oe__oe_ok$next 1'0 + assign \oper_l__write_cr__data$next 3'000 + assign \oper_l__write_cr__ok$next 1'0 + assign \oper_l__insn$next 32'00000000000000000000000000000000 end sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 10'0000000000 + update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_l__imm_data__imm_ok 1'0 + update \oper_l__lk 1'0 + update \oper_l__rc__rc 1'0 + update \oper_l__rc__rc_ok 1'0 + update \oper_l__oe__oe 1'0 + update \oper_l__oe__oe_ok 1'0 + update \oper_l__invert_a 1'0 + update \oper_l__zero_a 1'0 + update \oper_l__invert_out 1'0 + update \oper_l__write_cr__data 3'000 + update \oper_l__write_cr__ok 1'0 + update \oper_l__input_carry 2'00 + update \oper_l__output_carry 1'0 + update \oper_l__input_cr 1'0 + update \oper_l__output_cr 1'0 + update \oper_l__is_32bit 1'0 + update \oper_l__is_signed 1'0 + update \oper_l__data_len 4'0000 + update \oper_l__insn 32'00000000000000000000000000000000 + update \oper_l__byte_reverse 1'0 + update \oper_l__sign_extend 1'0 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__imm_data__imm \oper_l__imm_data__imm$next + update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next + update \oper_l__lk \oper_l__lk$next + update \oper_l__rc__rc \oper_l__rc__rc$next + update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next + update \oper_l__oe__oe \oper_l__oe__oe$next + update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next + update \oper_l__invert_a \oper_l__invert_a$next + update \oper_l__zero_a \oper_l__zero_a$next + update \oper_l__invert_out \oper_l__invert_out$next + update \oper_l__write_cr__data \oper_l__write_cr__data$next + update \oper_l__write_cr__ok \oper_l__write_cr__ok$next + update \oper_l__input_carry \oper_l__input_carry$next + update \oper_l__output_carry \oper_l__output_carry$next + update \oper_l__input_cr \oper_l__input_cr$next + update \oper_l__output_cr \oper_l__output_cr$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__is_signed \oper_l__is_signed$next + update \oper_l__data_len \oper_l__data_len$next + update \oper_l__insn \oper_l__insn$next + update \oper_l__byte_reverse \oper_l__byte_reverse$next + update \oper_l__sign_extend \oper_l__sign_extend$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $74 + parameter \WIDTH 65 + connect \A { \data_r0_l__o_ok \data_r0_l__o } + connect \B { \o_ok \o } + connect \S $72 + connect \Y $71 + end + process $group_73 + assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__o_ok 1'0 + assign { \data_r0__o_ok \data_r0__o } $71 + sync init + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $69 + wire width 1 $75 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $70 + cell $reduce_bool $76 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $69 + connect \Y $75 end - process $group_73 + process $group_75 assign \data_r0_l__o$next \data_r0_l__o assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -48493,62 +48521,62 @@ module \alu0 update \data_r0_l__o \data_r0_l__o$next update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 5 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $79 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $71 + connect \Y $78 end - process $group_75 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r0__o_ok \data_r0__o } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 5 + connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } + connect \B { \cr_a_ok \cr_a } + connect \S $78 + connect \Y $77 + end + process $group_77 + assign \data_r1__cr_a 4'0000 + assign \data_r1__cr_a_ok 1'0 + assign { \data_r1__cr_a_ok \data_r1__cr_a } $77 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $73 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $74 + cell $reduce_bool $82 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $73 + connect \Y $81 end - process $group_77 + process $group_79 assign \data_r1_l__cr_a$next \data_r1_l__cr_a assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -48562,62 +48590,62 @@ module \alu0 update \data_r1_l__cr_a \data_r1_l__cr_a$next update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 3 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $85 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $75 + connect \Y $84 end - process $group_79 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r1__cr_a_ok \data_r1__cr_a } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r1__cr_a_ok \data_r1__cr_a } { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 3 + connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } + connect \B { \xer_ca_ok \xer_ca } + connect \S $84 + connect \Y $83 + end + process $group_81 + assign \data_r2__xer_ca 2'00 + assign \data_r2__xer_ca_ok 1'0 + assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r2_l__xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r2_l__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $77 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $78 + cell $reduce_bool $88 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $77 + connect \Y $87 end - process $group_81 + process $group_83 assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -48631,62 +48659,62 @@ module \alu0 update \data_r2_l__xer_ca \data_r2_l__xer_ca$next update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 2 \data_r3__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r3_l__xer_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r3_l__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 3 $89 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $90 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $91 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $79 + connect \Y $90 end - process $group_83 - assign \data_r2__xer_ca 2'00 - assign \data_r2__xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \xer_ca_ok \xer_ca } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $92 + parameter \WIDTH 3 + connect \A { \data_r3_l__xer_ov_ok \data_r3_l__xer_ov } + connect \B { \xer_ov_ok \xer_ov } + connect \S $90 + connect \Y $89 + end + process $group_85 + assign \data_r3__xer_ov 2'00 + assign \data_r3__xer_ov_ok 1'0 + assign { \data_r3__xer_ov_ok \data_r3__xer_ov } $89 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r3_l__xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r3_l__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r3_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r3_l__xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $81 + wire width 1 $93 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $82 + cell $reduce_bool $94 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $81 + connect \Y $93 end - process $group_85 + process $group_87 assign \data_r3_l__xer_ov$next \data_r3_l__xer_ov assign \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov$next } { \xer_ov_ok \xer_ov } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -48700,62 +48728,62 @@ module \alu0 update \data_r3_l__xer_ov \data_r3_l__xer_ov$next update \data_r3_l__xer_ov_ok \data_r3_l__xer_ov_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 2 \data_r3__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r3__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r4__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $95 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $96 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $97 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $83 + connect \Y $96 end - process $group_87 - assign \data_r3__xer_ov 2'00 - assign \data_r3__xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r3__xer_ov_ok \data_r3__xer_ov } { \xer_ov_ok \xer_ov } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r3__xer_ov_ok \data_r3__xer_ov } { \data_r3_l__xer_ov_ok \data_r3_l__xer_ov } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $98 + parameter \WIDTH 2 + connect \A { \data_r4_l__xer_so_ok \data_r4_l__xer_so } + connect \B { \xer_so_ok \xer_so } + connect \S $96 + connect \Y $95 + end + process $group_89 + assign \data_r4__xer_so 1'0 + assign \data_r4__xer_so_ok 1'0 + assign { \data_r4__xer_so_ok \data_r4__xer_so } $95 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r4_l__xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r4_l__xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r4_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r4_l__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $85 + wire width 1 $99 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $86 + cell $reduce_bool $100 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $85 + connect \Y $99 end - process $group_89 + process $group_91 assign \data_r4_l__xer_so$next \data_r4_l__xer_so assign \data_r4_l__xer_so_ok$next \data_r4_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $99 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r4_l__xer_so_ok$next \data_r4_l__xer_so$next } { \xer_so_ok \xer_so } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -48769,284 +48797,256 @@ module \alu0 update \data_r4_l__xer_so \data_r4_l__xer_so$next update \data_r4_l__xer_so_ok \data_r4_l__xer_so_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r4__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r4__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $87 - end - process $group_91 - assign \data_r4__xer_so 1'0 - assign \data_r4__xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r4__xer_so_ok \data_r4__xer_so } { \xer_so_ok \xer_so } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r4__xer_so_ok \data_r4__xer_so } { \data_r4_l__xer_so_ok \data_r4_l__xer_so } - end - sync init - end process $group_93 assign \wrmask 5'00000 assign \wrmask { \data_r4__xer_so_ok \data_r3__xer_ov_ok \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok } sync init end process $group_94 - assign \alu_op__insn_type 7'0000000 - assign \alu_op__fn_unit 10'0000000000 - assign \alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok 1'0 - assign \alu_op__lk 1'0 - assign \alu_op__rc__rc 1'0 - assign \alu_op__rc__rc_ok 1'0 - assign \alu_op__oe__oe 1'0 - assign \alu_op__oe__oe_ok 1'0 - assign \alu_op__invert_a 1'0 - assign \alu_op__zero_a 1'0 - assign \alu_op__invert_out 1'0 - assign \alu_op__write_cr__data 3'000 - assign \alu_op__write_cr__ok 1'0 - assign \alu_op__input_carry 2'00 - assign \alu_op__output_carry 1'0 - assign \alu_op__input_cr 1'0 - assign \alu_op__output_cr 1'0 - assign \alu_op__is_32bit 1'0 - assign \alu_op__is_signed 1'0 - assign \alu_op__data_len 4'0000 - assign \alu_op__insn 32'00000000000000000000000000000000 - assign \alu_op__byte_reverse 1'0 - assign \alu_op__sign_extend 1'0 - assign { \alu_op__sign_extend \alu_op__byte_reverse \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_cr \alu_op__input_cr \alu_op__output_carry \alu_op__input_carry { \alu_op__write_cr__ok \alu_op__write_cr__data } \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } \alu_op__lk { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + assign \alu_alu0_op__insn_type 7'0000000 + assign \alu_alu0_op__fn_unit 10'0000000000 + assign \alu_alu0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_alu0_op__imm_data__imm_ok 1'0 + assign \alu_alu0_op__lk 1'0 + assign \alu_alu0_op__rc__rc 1'0 + assign \alu_alu0_op__rc__rc_ok 1'0 + assign \alu_alu0_op__oe__oe 1'0 + assign \alu_alu0_op__oe__oe_ok 1'0 + assign \alu_alu0_op__invert_a 1'0 + assign \alu_alu0_op__zero_a 1'0 + assign \alu_alu0_op__invert_out 1'0 + assign \alu_alu0_op__write_cr__data 3'000 + assign \alu_alu0_op__write_cr__ok 1'0 + assign \alu_alu0_op__input_carry 2'00 + assign \alu_alu0_op__output_carry 1'0 + assign \alu_alu0_op__input_cr 1'0 + assign \alu_alu0_op__output_cr 1'0 + assign \alu_alu0_op__is_32bit 1'0 + assign \alu_alu0_op__is_signed 1'0 + assign \alu_alu0_op__data_len 4'0000 + assign \alu_alu0_op__insn 32'00000000000000000000000000000000 + assign \alu_alu0_op__byte_reverse 1'0 + assign \alu_alu0_op__sign_extend 1'0 + assign { \alu_alu0_op__sign_extend \alu_alu0_op__byte_reverse \alu_alu0_op__insn \alu_alu0_op__data_len \alu_alu0_op__is_signed \alu_alu0_op__is_32bit \alu_alu0_op__output_cr \alu_alu0_op__input_cr \alu_alu0_op__output_carry \alu_alu0_op__input_carry { \alu_alu0_op__write_cr__ok \alu_alu0_op__write_cr__data } \alu_alu0_op__invert_out \alu_alu0_op__zero_a \alu_alu0_op__invert_a { \alu_alu0_op__oe__oe_ok \alu_alu0_op__oe__oe } { \alu_alu0_op__rc__rc_ok \alu_alu0_op__rc__rc } \alu_alu0_op__lk { \alu_alu0_op__imm_data__imm_ok \alu_alu0_op__imm_data__imm } \alu_alu0_op__fn_unit \alu_alu0_op__insn_type } { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 $89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - cell $mux $90 + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $102 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \oper_r__zero_a - connect \Y $89 + connect \Y $101 end process $group_118 assign \src_sel 1'0 - assign \src_sel $89 + assign \src_sel $101 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 64 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $104 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $91 + connect \Y $103 end process $group_119 assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $91 + assign \src_or_imm $103 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 1 \src_sel$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - cell $mux $95 + wire width 1 \src_sel$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $107 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \oper_r__imm_data__imm_ok - connect \Y $94 + connect \Y $106 end process $group_120 - assign \src_sel$93 1'0 - assign \src_sel$93 $94 + assign \src_sel$105 1'0 + assign \src_sel$105 $106 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" - wire width 64 \src_or_imm$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 64 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" + wire width 64 \src_or_imm$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $110 parameter \WIDTH 64 connect \A \src2_i connect \B \oper_r__imm_data__imm connect \S \oper_r__imm_data__imm_ok - connect \Y $97 + connect \Y $109 end process $group_121 - assign \src_or_imm$96 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$96 $97 + assign \src_or_imm$108 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$108 $109 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $112 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $111 + end process $group_122 + assign \alu_alu0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_alu0_ra $111 + sync init + end + process $group_123 assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r0$next \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r0 \src_r0$next end - process $group_123 - assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_ra \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_ra \src_r0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $114 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$108 + connect \S \src_sel$105 + connect \Y $113 + end process $group_124 + assign \alu_alu0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_alu0_rb $113 + sync init + end + process $group_125 assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel$93 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel$105 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r1$next \src_or_imm$96 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case + assign \src_r1$next \src_or_imm$108 end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r1 \src_r1$next end - process $group_125 - assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel$93 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_rb \src_or_imm$96 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_rb \src_r1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 1 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $116 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $115 + end process $group_126 + assign \alu_alu0_xer_so 1'0 + assign \alu_alu0_xer_so $115 + sync init + end + process $group_127 assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r2$next \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r2 1'0 sync posedge \clk update \src_r2 \src_r2$next end - process $group_127 - assign \alu_xer_so 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_xer_so \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_xer_so \src_r2 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 2 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 2 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $118 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $117 + end process $group_128 + assign \alu_alu0_xer_ca 2'00 + assign \alu_alu0_xer_ca $117 + sync init + end + process $group_129 assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r3$next \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r3 2'00 sync posedge \clk update \src_r3 \src_r3$next end - process $group_129 - assign \alu_xer_ca 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_xer_ca \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_xer_ca \src_r3 - end - sync init - end process $group_130 - assign \alu_p_valid_i 1'0 - assign \alu_p_valid_i \alui_l_q_alui + assign \alu_alu0_p_valid_i 1'0 + assign \alu_alu0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - cell $and $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_p_ready_o + connect \A \alu_alu0_p_ready_o connect \B \alui_l_q_alui - connect \Y $99 + connect \Y $119 end process $group_131 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $99 + assign \alui_l_r_alui$next $119 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -49063,26 +49063,26 @@ module \alu0 sync init end process $group_133 - assign \alu_n_ready_i 1'0 - assign \alu_n_ready_i \alu_l_q_alu + assign \alu_alu0_n_ready_i 1'0 + assign \alu_alu0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + cell $and $122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_alu0_n_valid_o connect \B \alu_l_q_alu - connect \Y $101 + connect \Y $121 end process $group_134 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $101 + assign \alu_l_r_alu$next $121 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -49103,10 +49103,10 @@ module \alu0 assign \busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $124 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -49114,73 +49114,73 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \busy_o \busy_o \busy_o \busy_o } - connect \Y $103 + connect \Y $123 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - cell $not $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \oper_r__zero_a - connect \Y $105 + connect \Y $125 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - cell $not $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \oper_r__imm_data__imm_ok - connect \Y $107 + connect \Y $127 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $103 - connect \B { 1'1 1'1 $107 $105 } - connect \Y $109 + connect \A $123 + connect \B { 1'1 1'1 $127 $125 } + connect \Y $129 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $not $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $not $132 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \rdmaskn - connect \Y $111 + connect \Y $131 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $134 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $109 - connect \B $111 - connect \Y $113 + connect \A $129 + connect \B $131 + connect \Y $133 end process $group_137 assign \rd__rel 4'0000 - assign \rd__rel $113 + assign \rd__rel $133 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -49188,12 +49188,12 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $115 + connect \Y $135 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -49201,12 +49201,12 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $117 + connect \Y $137 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -49214,12 +49214,12 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $119 + connect \Y $139 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -49227,12 +49227,12 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $121 + connect \Y $141 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -49240,44 +49240,44 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $123 + connect \Y $143 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 5 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 5 $145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $146 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \req_l_q_req - connect \B { $115 $117 $119 $121 $123 } - connect \Y $125 + connect \B { $135 $137 $139 $141 $143 } + connect \Y $145 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 5 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 5 $147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $148 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $125 + connect \A $145 connect \B \wrmask - connect \Y $127 + connect \Y $147 end process $group_138 assign \wr__rel 5'00000 - assign \wr__rel $127 + assign \wr__rel $147 sync init end process $group_139 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] end @@ -49287,9 +49287,9 @@ module \alu0 wire width 4 \dest2_o process $group_140 assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] end @@ -49299,9 +49299,9 @@ module \alu0 wire width 2 \dest3_o process $group_141 assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] end @@ -49311,9 +49311,9 @@ module \alu0 wire width 2 \dest4_o process $group_142 assign \dest4_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0] end @@ -49323,9 +49323,9 @@ module \alu0 wire width 1 \dest5_o process $group_143 assign \dest5_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0] end @@ -49333,8 +49333,8 @@ module \alu0 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.p" -module \p$4 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" +module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -49361,8 +49361,8 @@ module \p$4 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.n" -module \n$5 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" +module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -49389,8 +49389,8 @@ module \n$5 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe.p" -module \p$7 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" +module \p$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -49417,8 +49417,8 @@ module \p$7 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe.n" -module \n$8 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" +module \n$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -49445,8 +49445,8 @@ module \n$8 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe.main" -module \main$9 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" +module \main$8 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -50309,8 +50309,8 @@ module \main$9 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe" -module \pipe$6 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" +module \pipe$5 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -50561,11 +50561,11 @@ module \pipe$6 wire width 1 output 29 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \cr_a_ok$next - cell \p$7 \p + cell \p$6 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$8 \n + cell \n$7 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -50783,7 +50783,7 @@ module \pipe$6 wire width 4 \main_cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_cr_a_ok - cell \main$9 \main + cell \main$8 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -51179,8 +51179,8 @@ module \pipe$6 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu" -module \alu$3 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" +module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -51310,11 +51310,11 @@ module \alu$3 wire width 1 input 21 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 22 \p_ready_o - cell \p$4 \p + cell \p$3 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$5 \n + cell \n$4 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -51540,7 +51540,7 @@ module \alu$3 wire width 4 \pipe_cr_a$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_cr_a_ok - cell \pipe$6 \pipe + cell \pipe$5 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -51769,24 +51769,24 @@ module \alu$3 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" -module \src_l$10 +module \src_l$9 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 3 \r_src + wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51794,9 +51794,9 @@ module \src_l$10 connect \A \r_src connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51807,9 +51807,9 @@ module \src_l$10 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51833,9 +51833,9 @@ module \src_l$10 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51843,9 +51843,9 @@ module \src_l$10 connect \A \r_src connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51856,9 +51856,9 @@ module \src_l$10 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51874,11 +51874,11 @@ module \src_l$10 assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51891,11 +51891,11 @@ module \src_l$10 assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 6 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -51914,24 +51914,24 @@ module \src_l$10 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" -module \opc_l$11 +module \opc_l$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_opc + wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -51939,9 +51939,9 @@ module \opc_l$11 connect \A \r_opc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -51952,9 +51952,9 @@ module \opc_l$11 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -51978,9 +51978,9 @@ module \opc_l$11 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -51988,9 +51988,9 @@ module \opc_l$11 connect \A \r_opc connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52001,9 +52001,9 @@ module \opc_l$11 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52019,11 +52019,11 @@ module \opc_l$11 assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52036,11 +52036,11 @@ module \opc_l$11 assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52059,24 +52059,24 @@ module \opc_l$11 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" -module \req_l$12 +module \req_l$11 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52084,9 +52084,9 @@ module \req_l$12 connect \A \r_req connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52097,9 +52097,9 @@ module \req_l$12 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52123,9 +52123,9 @@ module \req_l$12 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52133,9 +52133,9 @@ module \req_l$12 connect \A \r_req connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52146,9 +52146,9 @@ module \req_l$12 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52164,11 +52164,11 @@ module \req_l$12 assign \q_req $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52181,11 +52181,11 @@ module \req_l$12 assign \qn_req $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -52204,22 +52204,22 @@ module \req_l$12 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" -module \rst_l$13 +module \rst_l$12 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52227,9 +52227,9 @@ module \rst_l$13 connect \A \r_rst connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52240,9 +52240,9 @@ module \rst_l$13 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52266,11 +52266,11 @@ module \rst_l$13 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52278,9 +52278,9 @@ module \rst_l$13 connect \A \r_rst connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52291,9 +52291,9 @@ module \rst_l$13 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52309,11 +52309,11 @@ module \rst_l$13 assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52326,11 +52326,11 @@ module \rst_l$13 assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52349,24 +52349,24 @@ module \rst_l$13 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" -module \rok_l$14 +module \rok_l$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52374,9 +52374,9 @@ module \rok_l$14 connect \A \r_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52387,9 +52387,9 @@ module \rok_l$14 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52413,9 +52413,9 @@ module \rok_l$14 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52423,9 +52423,9 @@ module \rok_l$14 connect \A \r_rdok connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52436,9 +52436,9 @@ module \rok_l$14 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52454,11 +52454,11 @@ module \rok_l$14 assign \q_rdok $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52471,11 +52471,11 @@ module \rok_l$14 assign \qn_rdok $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52494,24 +52494,24 @@ module \rok_l$14 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" -module \alui_l$15 +module \alui_l$14 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52519,9 +52519,9 @@ module \alui_l$15 connect \A \r_alui connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52532,9 +52532,9 @@ module \alui_l$15 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52558,9 +52558,9 @@ module \alui_l$15 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52568,9 +52568,9 @@ module \alui_l$15 connect \A \r_alui connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52581,9 +52581,9 @@ module \alui_l$15 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52599,11 +52599,11 @@ module \alui_l$15 assign \q_alui $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52616,11 +52616,11 @@ module \alui_l$15 assign \qn_alui $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52639,24 +52639,24 @@ module \alui_l$15 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" -module \alu_l$16 +module \alu_l$15 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52664,9 +52664,9 @@ module \alu_l$16 connect \A \r_alu connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52677,9 +52677,9 @@ module \alu_l$16 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52703,9 +52703,9 @@ module \alu_l$16 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52713,9 +52713,9 @@ module \alu_l$16 connect \A \r_alu connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52726,9 +52726,9 @@ module \alu_l$16 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52744,11 +52744,11 @@ module \alu_l$16 assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52761,11 +52761,11 @@ module \alu_l$16 assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -52927,9 +52927,9 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" wire width 64 output 28 \dest1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" - wire width 1 \alu_n_valid_o + wire width 1 \alu_cr0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" - wire width 1 \alu_n_ready_i + wire width 1 \alu_cr0_n_ready_i attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -53003,7 +53003,7 @@ module \cr0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 7 \alu_op__insn_type + wire width 7 \alu_cr0_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -53016,30 +53016,30 @@ module \cr0 attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \alu_op__fn_unit + wire width 10 \alu_cr0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 32 \alu_op__insn + wire width 32 \alu_cr0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 \alu_op__read_cr_whole + wire width 1 \alu_cr0_op__read_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 \alu_op__write_cr_whole + wire width 1 \alu_cr0_op__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_ra + wire width 64 \alu_cr0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_rb + wire width 64 \alu_cr0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 32 \alu_full_cr + wire width 32 \alu_cr0_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 4 \alu_cr_a + wire width 4 \alu_cr0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 4 \alu_cr_b + wire width 4 \alu_cr0_cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 4 \alu_cr_c + wire width 4 \alu_cr0_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" - wire width 1 \alu_p_valid_i + wire width 1 \alu_cr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" - wire width 1 \alu_p_ready_o - cell \alu$3 \alu + wire width 1 \alu_cr0_p_ready_o + cell \alu_cr0 \alu_cr0 connect \rst \rst connect \clk \clk connect \o_ok \o_ok @@ -53048,129 +53048,129 @@ module \cr0 connect \full_cr \full_cr connect \cr_a_ok \cr_a_ok connect \cr_a \cr_a - connect \n_valid_o \alu_n_valid_o - connect \n_ready_i \alu_n_ready_i - connect \op__insn_type \alu_op__insn_type - connect \op__fn_unit \alu_op__fn_unit - connect \op__insn \alu_op__insn - connect \op__read_cr_whole \alu_op__read_cr_whole - connect \op__write_cr_whole \alu_op__write_cr_whole - connect \ra \alu_ra - connect \rb \alu_rb - connect \full_cr$1 \alu_full_cr - connect \cr_a$2 \alu_cr_a - connect \cr_b \alu_cr_b - connect \cr_c \alu_cr_c - connect \p_valid_i \alu_p_valid_i - connect \p_ready_o \alu_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + connect \n_valid_o \alu_cr0_n_valid_o + connect \n_ready_i \alu_cr0_n_ready_i + connect \op__insn_type \alu_cr0_op__insn_type + connect \op__fn_unit \alu_cr0_op__fn_unit + connect \op__insn \alu_cr0_op__insn + connect \op__read_cr_whole \alu_cr0_op__read_cr_whole + connect \op__write_cr_whole \alu_cr0_op__write_cr_whole + connect \ra \alu_cr0_ra + connect \rb \alu_cr0_rb + connect \full_cr$1 \alu_cr0_full_cr + connect \cr_a$2 \alu_cr0_cr_a + connect \cr_b \alu_cr0_cr_b + connect \cr_c \alu_cr0_cr_c + connect \p_valid_i \alu_cr0_p_valid_i + connect \p_ready_o \alu_cr0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 6 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 6 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 6 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 \src_l_q_src - cell \src_l$10 \src_l + cell \src_l$9 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src connect \r_src \src_l_r_src connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$11 \opc_l + cell \opc_l$10 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc connect \r_opc \opc_l_r_opc connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req - cell \req_l$12 \req_l + cell \req_l$11 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req connect \s_req \req_l_s_req connect \r_req \req_l_r_req end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$13 \rst_l + cell \rst_l$12 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst connect \r_rst \rst_l_r_rst end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$14 \rok_l + cell \rok_l$13 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok connect \s_rdok \rok_l_s_rdok connect \r_rdok \rok_l_r_rdok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$15 \alui_l + cell \alui_l$14 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$16 \alu_l + cell \alu_l$15 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177" - wire width 1 \all_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53181,11 +53181,11 @@ module \cr0 connect \B \rok_l_q_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 6 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -53193,9 +53193,9 @@ module \cr0 connect \A \rd__rel connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 6 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $or $7 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -53206,7 +53206,7 @@ module \cr0 connect \B \rd__go connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $reduce_and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -53214,9 +53214,9 @@ module \cr0 connect \A $6 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53232,9 +53232,9 @@ module \cr0 assign \all_rd $9 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -53244,11 +53244,11 @@ module \cr0 sync posedge \clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184" wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $not $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53256,9 +53256,9 @@ module \cr0 connect \A \all_rd_dly connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $and $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53274,16 +53274,16 @@ module \cr0 assign \all_rd_pulse $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 \alu_done process $group_3 assign \alu_done 1'0 - assign \alu_done \alu_n_valid_o + assign \alu_done \alu_cr0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly$next process $group_4 assign \alu_done_dly$next \alu_done_dly @@ -53293,11 +53293,11 @@ module \cr0 sync posedge \clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $not $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53305,9 +53305,9 @@ module \cr0 connect \A \alu_done_dly connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $and $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53323,20 +53323,20 @@ module \cr0 assign \alu_pulse $17 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire width 3 \alu_pulsem process $group_6 assign \alu_pulsem 3'000 assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" wire width 3 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53362,15 +53362,15 @@ module \cr0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire width 1 \done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" wire width 3 \wrmask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53378,9 +53378,9 @@ module \cr0 connect \A \wrmask connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53391,7 +53391,7 @@ module \cr0 connect \B $23 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $reduce_bool $27 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53399,7 +53399,7 @@ module \cr0 connect \A $25 connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53407,9 +53407,9 @@ module \cr0 connect \A $22 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53425,11 +53425,11 @@ module \cr0 assign \done_o $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53437,9 +53437,9 @@ module \cr0 connect \A \wr__go connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $34 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53447,9 +53447,9 @@ module \cr0 connect \A \prev_wr_go connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53465,21 +53465,21 @@ module \cr0 assign \wr_any $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_ready_i + connect \A \alu_cr0_n_ready_i connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53490,9 +53490,9 @@ module \cr0 connect \B $37 connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53503,9 +53503,9 @@ module \cr0 connect \B \wrmask connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53516,9 +53516,9 @@ module \cr0 connect \B 1'0 connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53529,9 +53529,9 @@ module \cr0 connect \B $43 connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53542,9 +53542,9 @@ module \cr0 connect \B 1'0 connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53552,12 +53552,12 @@ module \cr0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $47 - connect \B \alu_n_ready_i + connect \B \alu_cr0_n_ready_i connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53565,12 +53565,12 @@ module \cr0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_n_valid_o + connect \B \alu_cr0_n_valid_o connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53584,19 +53584,19 @@ module \cr0 process $group_10 assign \req_done 1'0 assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" cell $or $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53612,11 +53612,11 @@ module \cr0 assign \reset $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" cell $or $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -53632,11 +53632,11 @@ module \cr0 assign \rst_r $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" cell $or $60 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53652,11 +53652,11 @@ module \cr0 assign \reset_w $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" wire width 6 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 6 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" cell $or $62 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -53677,16 +53677,16 @@ module \cr0 assign \rok_l_s_rdok \issue_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_cr0_n_valid_o connect \B \busy_o connect \Y $63 end @@ -53765,9 +53765,9 @@ module \cr0 sync posedge \clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53783,9 +53783,9 @@ module \cr0 assign \req_l_s_req $65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" cell $or $68 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -53801,53 +53801,6 @@ module \cr0 assign \req_l_r_req $67 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__read_cr_whole$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr_whole$next - process $group_25 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__insn$next \oper_l__insn - assign \oper_l__read_cr_whole$next \oper_l__read_cr_whole - assign \oper_l__write_cr_whole$next \oper_l__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \oper_l__write_cr_whole$next \oper_l__read_cr_whole$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 - update \oper_l__insn 32'00000000000000000000000000000000 - update \oper_l__read_cr_whole 1'0 - update \oper_l__write_cr_whole 1'0 - sync posedge \clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__insn \oper_l__insn$next - update \oper_l__read_cr_whole \oper_l__read_cr_whole$next - update \oper_l__write_cr_whole \oper_l__write_cr_whole$next - end attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -53941,51 +53894,126 @@ module \cr0 wire width 1 \oper_r__read_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 1 \oper_r__write_cr_whole - process $group_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__read_cr_whole$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr_whole$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 51 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $70 + parameter \WIDTH 51 + connect \A { \oper_l__write_cr_whole \oper_l__read_cr_whole \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } + connect \S \issue_i + connect \Y $69 + end + process $group_25 assign \oper_r__insn_type 7'0000000 assign \oper_r__fn_unit 10'0000000000 assign \oper_r__insn 32'00000000000000000000000000000000 assign \oper_r__read_cr_whole 1'0 assign \oper_r__write_cr_whole 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $69 + sync init + end + process $group_30 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__insn$next \oper_l__insn + assign \oper_l__read_cr_whole$next \oper_l__read_cr_whole + assign \oper_l__write_cr_whole$next \oper_l__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_l__write_cr_whole \oper_l__read_cr_whole \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } + assign { \oper_l__write_cr_whole$next \oper_l__read_cr_whole$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } end sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 10'0000000000 + update \oper_l__insn 32'00000000000000000000000000000000 + update \oper_l__read_cr_whole 1'0 + update \oper_l__write_cr_whole 1'0 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__insn \oper_l__insn$next + update \oper_l__read_cr_whole \oper_l__read_cr_whole$next + update \oper_l__write_cr_whole \oper_l__write_cr_whole$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $74 + parameter \WIDTH 65 + connect \A { \data_r0_l__o_ok \data_r0_l__o } + connect \B { \o_ok \o } + connect \S $72 + connect \Y $71 + end + process $group_35 + assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__o_ok 1'0 + assign { \data_r0__o_ok \data_r0__o } $71 + sync init + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $69 + wire width 1 $75 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $70 + cell $reduce_bool $76 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $69 + connect \Y $75 end - process $group_35 + process $group_37 assign \data_r0_l__o$next \data_r0_l__o assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -53999,62 +54027,62 @@ module \cr0 update \data_r0_l__o \data_r0_l__o$next update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 32 \data_r1__full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r1__full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \data_r1_l__full_cr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \data_r1_l__full_cr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__full_cr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 33 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $79 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $71 + connect \Y $78 end - process $group_37 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r0__o_ok \data_r0__o } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 33 + connect \A { \data_r1_l__full_cr_ok \data_r1_l__full_cr } + connect \B { \full_cr_ok \full_cr } + connect \S $78 + connect \Y $77 + end + process $group_39 + assign \data_r1__full_cr 32'00000000000000000000000000000000 + assign \data_r1__full_cr_ok 1'0 + assign { \data_r1__full_cr_ok \data_r1__full_cr } $77 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \data_r1_l__full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \data_r1_l__full_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__full_cr_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $73 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $74 + cell $reduce_bool $82 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $73 + connect \Y $81 end - process $group_39 + process $group_41 assign \data_r1_l__full_cr$next \data_r1_l__full_cr assign \data_r1_l__full_cr_ok$next \data_r1_l__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r1_l__full_cr_ok$next \data_r1_l__full_cr$next } { \full_cr_ok \full_cr } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -54068,62 +54096,62 @@ module \cr0 update \data_r1_l__full_cr \data_r1_l__full_cr$next update \data_r1_l__full_cr_ok \data_r1_l__full_cr_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 32 \data_r1__full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r1__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 4 \data_r2__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r2__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r2_l__cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r2_l__cr_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 5 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $85 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $75 + connect \Y $84 end - process $group_41 - assign \data_r1__full_cr 32'00000000000000000000000000000000 - assign \data_r1__full_cr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r1__full_cr_ok \data_r1__full_cr } { \full_cr_ok \full_cr } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r1__full_cr_ok \data_r1__full_cr } { \data_r1_l__full_cr_ok \data_r1_l__full_cr } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 5 + connect \A { \data_r2_l__cr_a_ok \data_r2_l__cr_a } + connect \B { \cr_a_ok \cr_a } + connect \S $84 + connect \Y $83 + end + process $group_43 + assign \data_r2__cr_a 4'0000 + assign \data_r2__cr_a_ok 1'0 + assign { \data_r2__cr_a_ok \data_r2__cr_a } $83 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r2_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r2_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $77 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $78 + cell $reduce_bool $88 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $77 + connect \Y $87 end - process $group_43 + process $group_45 assign \data_r2_l__cr_a$next \data_r2_l__cr_a assign \data_r2_l__cr_a_ok$next \data_r2_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r2_l__cr_a_ok$next \data_r2_l__cr_a$next } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -54137,261 +54165,233 @@ module \cr0 update \data_r2_l__cr_a \data_r2_l__cr_a$next update \data_r2_l__cr_a_ok \data_r2_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 4 \data_r2__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r2__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $79 - end - process $group_45 - assign \data_r2__cr_a 4'0000 - assign \data_r2__cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r2__cr_a_ok \data_r2__cr_a } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r2__cr_a_ok \data_r2__cr_a } { \data_r2_l__cr_a_ok \data_r2_l__cr_a } - end - sync init - end process $group_47 assign \wrmask 3'000 assign \wrmask { \data_r2__cr_a_ok \data_r1__full_cr_ok \data_r0__o_ok } sync init end process $group_48 - assign \alu_op__insn_type 7'0000000 - assign \alu_op__fn_unit 10'0000000000 - assign \alu_op__insn 32'00000000000000000000000000000000 - assign \alu_op__read_cr_whole 1'0 - assign \alu_op__write_cr_whole 1'0 - assign { \alu_op__write_cr_whole \alu_op__read_cr_whole \alu_op__insn \alu_op__fn_unit \alu_op__insn_type } { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } + assign \alu_cr0_op__insn_type 7'0000000 + assign \alu_cr0_op__fn_unit 10'0000000000 + assign \alu_cr0_op__insn 32'00000000000000000000000000000000 + assign \alu_cr0_op__read_cr_whole 1'0 + assign \alu_cr0_op__write_cr_whole 1'0 + assign { \alu_cr0_op__write_cr_whole \alu_cr0_op__read_cr_whole \alu_cr0_op__insn \alu_cr0_op__fn_unit \alu_cr0_op__insn_type } { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $90 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $89 + end process $group_53 + assign \alu_cr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_cr0_ra $89 + sync init + end + process $group_54 assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r0$next \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r0 \src_r0$next end - process $group_54 - assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_ra \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_ra \src_r0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $92 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $91 + end process $group_55 + assign \alu_cr0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_cr0_rb $91 + sync init + end + process $group_56 assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r1$next \src2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r1 \src_r1$next end - process $group_56 - assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_rb \src2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_rb \src_r1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 32 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 32 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 32 $93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $94 + parameter \WIDTH 32 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $93 + end process $group_57 + assign \alu_cr0_full_cr 32'00000000000000000000000000000000 + assign \alu_cr0_full_cr $93 + sync init + end + process $group_58 assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r2$next \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r2 32'00000000000000000000000000000000 sync posedge \clk update \src_r2 \src_r2$next end - process $group_58 - assign \alu_full_cr 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_full_cr \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_full_cr \src_r2 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $96 + parameter \WIDTH 4 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $95 + end process $group_59 + assign \alu_cr0_cr_a 4'0000 + assign \alu_cr0_cr_a $95 + sync init + end + process $group_60 assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r3$next \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r3 4'0000 sync posedge \clk update \src_r3 \src_r3$next end - process $group_60 - assign \alu_cr_a 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_cr_a \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_cr_a \src_r3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $98 + parameter \WIDTH 4 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $97 + end process $group_61 + assign \alu_cr0_cr_b 4'0000 + assign \alu_cr0_cr_b $97 + sync init + end + process $group_62 assign \src_r4$next \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r4$next \src5_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r4 4'0000 sync posedge \clk update \src_r4 \src_r4$next end - process $group_62 - assign \alu_cr_b 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_cr_b \src5_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_cr_b \src_r4 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r5$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $100 + parameter \WIDTH 4 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $99 + end process $group_63 + assign \alu_cr0_cr_c 4'0000 + assign \alu_cr0_cr_c $99 + sync init + end + process $group_64 assign \src_r5$next \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r5$next \src6_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r5 4'0000 sync posedge \clk update \src_r5 \src_r5$next end - process $group_64 - assign \alu_cr_c 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_cr_c \src6_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_cr_c \src_r5 - end - sync init - end process $group_65 - assign \alu_p_valid_i 1'0 - assign \alu_p_valid_i \alui_l_q_alui + assign \alu_cr0_p_valid_i 1'0 + assign \alu_cr0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - cell $and $82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + cell $and $102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_p_ready_o + connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $81 + connect \Y $101 end process $group_66 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $81 + assign \alui_l_r_alui$next $101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -54408,26 +54408,26 @@ module \cr0 sync init end process $group_68 - assign \alu_n_ready_i 1'0 - assign \alu_n_ready_i \alu_l_q_alu + assign \alu_cr0_n_ready_i 1'0 + assign \alu_cr0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + cell $and $104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $83 + connect \Y $103 end process $group_69 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $83 + assign \alu_l_r_alu$next $103 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -54448,10 +54448,10 @@ module \cr0 assign \busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $106 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -54459,53 +54459,53 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o } - connect \Y $85 + connect \Y $105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $108 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 - connect \A $85 + connect \A $105 connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } - connect \Y $87 + connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $not $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $not $110 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \rdmaskn - connect \Y $89 + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $112 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 - connect \A $87 - connect \B $89 - connect \Y $91 + connect \A $107 + connect \B $109 + connect \Y $111 end process $group_72 assign \rd__rel 6'000000 - assign \rd__rel $91 + assign \rd__rel $111 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54513,12 +54513,12 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $93 + connect \Y $113 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54526,12 +54526,12 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $95 + connect \Y $115 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54539,44 +54539,44 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $97 + connect \Y $117 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req - connect \B { $93 $95 $97 } - connect \Y $99 + connect \B { $113 $115 $117 } + connect \Y $119 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $122 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $99 + connect \A $119 connect \B \wrmask - connect \Y $101 + connect \Y $121 end process $group_73 assign \wr__rel 3'000 - assign \wr__rel $101 + assign \wr__rel $121 sync init end process $group_74 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] end @@ -54586,9 +54586,9 @@ module \cr0 wire width 32 \dest2_o process $group_75 assign \dest2_o 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest2_o { \data_r1__full_cr_ok \data_r1__full_cr } [31:0] end @@ -54598,9 +54598,9 @@ module \cr0 wire width 4 \dest3_o process $group_76 assign \dest3_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest3_o { \data_r2__cr_a_ok \data_r2__cr_a } [3:0] end @@ -54608,8 +54608,8 @@ module \cr0 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.p" -module \p$18 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" +module \p$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -54636,8 +54636,8 @@ module \p$18 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.n" -module \n$19 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" +module \n$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -54664,8 +54664,8 @@ module \n$19 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe.p" -module \p$21 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" +module \p$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -54692,8 +54692,8 @@ module \p$21 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe.n" -module \n$22 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" +module \n$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -54720,8 +54720,8 @@ module \n$22 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe.main" -module \main$23 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" +module \main$21 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -55429,8 +55429,8 @@ module \main$23 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe" -module \pipe$20 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" +module \pipe$18 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -55689,11 +55689,11 @@ module \pipe$20 wire width 1 output 31 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \nia_ok$next - cell \p$21 \p + cell \p$19 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$22 \n + cell \n$20 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -55915,7 +55915,7 @@ module \pipe$20 wire width 64 \main_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_nia_ok - cell \main$23 \main + cell \main$21 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -56323,8 +56323,8 @@ module \pipe$20 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu" -module \alu$17 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" +module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -56454,11 +56454,11 @@ module \alu$17 wire width 1 input 21 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 22 \p_ready_o - cell \p$18 \p + cell \p$16 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$19 \n + cell \n$17 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -56688,7 +56688,7 @@ module \alu$17 wire width 64 \pipe_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_nia_ok - cell \pipe$20 \pipe + cell \pipe$18 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -56917,24 +56917,24 @@ module \alu$17 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" -module \src_l$24 +module \src_l$22 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \r_src + wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -56942,9 +56942,9 @@ module \src_l$24 connect \A \r_src connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -56955,9 +56955,9 @@ module \src_l$24 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -56981,9 +56981,9 @@ module \src_l$24 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -56991,9 +56991,9 @@ module \src_l$24 connect \A \r_src connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -57004,9 +57004,9 @@ module \src_l$24 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -57022,11 +57022,11 @@ module \src_l$24 assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -57039,11 +57039,11 @@ module \src_l$24 assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -57062,24 +57062,24 @@ module \src_l$24 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" -module \opc_l$25 +module \opc_l$23 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_opc + wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57087,9 +57087,9 @@ module \opc_l$25 connect \A \r_opc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57100,9 +57100,9 @@ module \opc_l$25 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57126,9 +57126,9 @@ module \opc_l$25 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57136,9 +57136,9 @@ module \opc_l$25 connect \A \r_opc connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57149,9 +57149,9 @@ module \opc_l$25 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57167,11 +57167,11 @@ module \opc_l$25 assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57184,11 +57184,11 @@ module \opc_l$25 assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57207,24 +57207,24 @@ module \opc_l$25 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" -module \req_l$26 +module \req_l$24 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57232,9 +57232,9 @@ module \req_l$26 connect \A \r_req connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57245,9 +57245,9 @@ module \req_l$26 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57271,9 +57271,9 @@ module \req_l$26 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57281,9 +57281,9 @@ module \req_l$26 connect \A \r_req connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57294,9 +57294,9 @@ module \req_l$26 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57312,11 +57312,11 @@ module \req_l$26 assign \q_req $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57329,11 +57329,11 @@ module \req_l$26 assign \qn_req $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -57352,22 +57352,22 @@ module \req_l$26 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" -module \rst_l$27 +module \rst_l$25 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57375,9 +57375,9 @@ module \rst_l$27 connect \A \r_rst connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57388,9 +57388,9 @@ module \rst_l$27 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57414,11 +57414,11 @@ module \rst_l$27 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57426,9 +57426,9 @@ module \rst_l$27 connect \A \r_rst connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57439,9 +57439,9 @@ module \rst_l$27 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57457,11 +57457,11 @@ module \rst_l$27 assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57474,11 +57474,11 @@ module \rst_l$27 assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57497,24 +57497,24 @@ module \rst_l$27 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" -module \rok_l$28 +module \rok_l$26 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57522,9 +57522,9 @@ module \rok_l$28 connect \A \r_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57535,9 +57535,9 @@ module \rok_l$28 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57561,9 +57561,9 @@ module \rok_l$28 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57571,9 +57571,9 @@ module \rok_l$28 connect \A \r_rdok connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57584,9 +57584,9 @@ module \rok_l$28 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57602,11 +57602,11 @@ module \rok_l$28 assign \q_rdok $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57619,11 +57619,11 @@ module \rok_l$28 assign \qn_rdok $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57642,24 +57642,24 @@ module \rok_l$28 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" -module \alui_l$29 +module \alui_l$27 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57667,9 +57667,9 @@ module \alui_l$29 connect \A \r_alui connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57680,9 +57680,9 @@ module \alui_l$29 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57706,9 +57706,9 @@ module \alui_l$29 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57716,9 +57716,9 @@ module \alui_l$29 connect \A \r_alui connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57729,9 +57729,9 @@ module \alui_l$29 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57747,11 +57747,11 @@ module \alui_l$29 assign \q_alui $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57764,11 +57764,11 @@ module \alui_l$29 assign \qn_alui $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57787,24 +57787,24 @@ module \alui_l$29 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" -module \alu_l$30 +module \alu_l$28 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57812,9 +57812,9 @@ module \alu_l$30 connect \A \r_alu connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57825,9 +57825,9 @@ module \alu_l$30 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57851,9 +57851,9 @@ module \alu_l$30 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57861,9 +57861,9 @@ module \alu_l$30 connect \A \r_alu connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57874,9 +57874,9 @@ module \alu_l$30 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57892,11 +57892,11 @@ module \alu_l$30 assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -57909,11 +57909,11 @@ module \alu_l$30 assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58075,9 +58075,9 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" wire width 64 output 28 \dest1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" - wire width 1 \alu_n_valid_o + wire width 1 \alu_branch0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" - wire width 1 \alu_n_ready_i + wire width 1 \alu_branch0_n_ready_i attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -58151,7 +58151,7 @@ module \branch0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 7 \alu_op__insn_type + wire width 7 \alu_branch0_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -58164,30 +58164,30 @@ module \branch0 attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \alu_op__fn_unit + wire width 10 \alu_branch0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 64 \alu_op__imm_data__imm + wire width 64 \alu_branch0_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 \alu_op__imm_data__imm_ok + wire width 1 \alu_branch0_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 \alu_op__lk + wire width 1 \alu_branch0_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 \alu_op__is_32bit + wire width 1 \alu_branch0_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 32 \alu_op__insn + wire width 32 \alu_branch0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_spr1 + wire width 64 \alu_branch0_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_spr2 + wire width 64 \alu_branch0_spr2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 4 \alu_cr_a + wire width 4 \alu_branch0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_cia + wire width 64 \alu_branch0_cia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" - wire width 1 \alu_p_valid_i + wire width 1 \alu_branch0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" - wire width 1 \alu_p_ready_o - cell \alu$17 \alu + wire width 1 \alu_branch0_p_ready_o + cell \alu_branch0 \alu_branch0 connect \rst \rst connect \clk \clk connect \spr1_ok \spr1_ok @@ -58196,129 +58196,129 @@ module \branch0 connect \spr2 \spr2 connect \nia_ok \nia_ok connect \nia \nia - connect \n_valid_o \alu_n_valid_o - connect \n_ready_i \alu_n_ready_i - connect \op__insn_type \alu_op__insn_type - connect \op__fn_unit \alu_op__fn_unit - connect \op__imm_data__imm \alu_op__imm_data__imm - connect \op__imm_data__imm_ok \alu_op__imm_data__imm_ok - connect \op__lk \alu_op__lk - connect \op__is_32bit \alu_op__is_32bit - connect \op__insn \alu_op__insn - connect \spr1$1 \alu_spr1 - connect \spr2$2 \alu_spr2 - connect \cr_a \alu_cr_a - connect \cia \alu_cia - connect \p_valid_i \alu_p_valid_i - connect \p_ready_o \alu_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + connect \n_valid_o \alu_branch0_n_valid_o + connect \n_ready_i \alu_branch0_n_ready_i + connect \op__insn_type \alu_branch0_op__insn_type + connect \op__fn_unit \alu_branch0_op__fn_unit + connect \op__imm_data__imm \alu_branch0_op__imm_data__imm + connect \op__imm_data__imm_ok \alu_branch0_op__imm_data__imm_ok + connect \op__lk \alu_branch0_op__lk + connect \op__is_32bit \alu_branch0_op__is_32bit + connect \op__insn \alu_branch0_op__insn + connect \spr1$1 \alu_branch0_spr1 + connect \spr2$2 \alu_branch0_spr2 + connect \cr_a \alu_branch0_cr_a + connect \cia \alu_branch0_cia + connect \p_valid_i \alu_branch0_p_valid_i + connect \p_ready_o \alu_branch0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 4 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src - cell \src_l$24 \src_l + cell \src_l$22 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src connect \r_src \src_l_r_src connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$25 \opc_l + cell \opc_l$23 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc connect \r_opc \opc_l_r_opc connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req - cell \req_l$26 \req_l + cell \req_l$24 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req connect \s_req \req_l_s_req connect \r_req \req_l_r_req end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$27 \rst_l + cell \rst_l$25 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst connect \r_rst \rst_l_r_rst end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$28 \rok_l + cell \rok_l$26 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok connect \s_rdok \rok_l_s_rdok connect \r_rdok \rok_l_r_rdok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$29 \alui_l + cell \alui_l$27 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$30 \alu_l + cell \alu_l$28 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177" - wire width 1 \all_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58329,11 +58329,11 @@ module \branch0 connect \B \rok_l_q_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 4 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -58341,9 +58341,9 @@ module \branch0 connect \A \rd__rel connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 4 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $or $7 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -58354,7 +58354,7 @@ module \branch0 connect \B \rd__go connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $reduce_and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -58362,9 +58362,9 @@ module \branch0 connect \A $6 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58380,9 +58380,9 @@ module \branch0 assign \all_rd $9 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -58392,11 +58392,11 @@ module \branch0 sync posedge \clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184" wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $not $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58404,9 +58404,9 @@ module \branch0 connect \A \all_rd_dly connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $and $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58422,16 +58422,16 @@ module \branch0 assign \all_rd_pulse $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 \alu_done process $group_3 assign \alu_done 1'0 - assign \alu_done \alu_n_valid_o + assign \alu_done \alu_branch0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly$next process $group_4 assign \alu_done_dly$next \alu_done_dly @@ -58441,11 +58441,11 @@ module \branch0 sync posedge \clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $not $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58453,9 +58453,9 @@ module \branch0 connect \A \alu_done_dly connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $and $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58471,20 +58471,20 @@ module \branch0 assign \alu_pulse $17 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire width 3 \alu_pulsem process $group_6 assign \alu_pulsem 3'000 assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" wire width 3 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58510,15 +58510,15 @@ module \branch0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire width 1 \done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" wire width 3 \wrmask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58526,9 +58526,9 @@ module \branch0 connect \A \wrmask connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58539,7 +58539,7 @@ module \branch0 connect \B $23 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $reduce_bool $27 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58547,7 +58547,7 @@ module \branch0 connect \A $25 connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58555,9 +58555,9 @@ module \branch0 connect \A $22 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58573,11 +58573,11 @@ module \branch0 assign \done_o $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58585,9 +58585,9 @@ module \branch0 connect \A \wr__go connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $34 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58595,9 +58595,9 @@ module \branch0 connect \A \prev_wr_go connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58613,21 +58613,21 @@ module \branch0 assign \wr_any $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_ready_i + connect \A \alu_branch0_n_ready_i connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58638,9 +58638,9 @@ module \branch0 connect \B $37 connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58651,9 +58651,9 @@ module \branch0 connect \B \wrmask connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58664,9 +58664,9 @@ module \branch0 connect \B 1'0 connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58677,9 +58677,9 @@ module \branch0 connect \B $43 connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58690,9 +58690,9 @@ module \branch0 connect \B 1'0 connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58700,12 +58700,12 @@ module \branch0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $47 - connect \B \alu_n_ready_i + connect \B \alu_branch0_n_ready_i connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58713,12 +58713,12 @@ module \branch0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_n_valid_o + connect \B \alu_branch0_n_valid_o connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58732,19 +58732,19 @@ module \branch0 process $group_10 assign \req_done 1'0 assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" cell $or $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58760,11 +58760,11 @@ module \branch0 assign \reset $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" cell $or $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -58780,11 +58780,11 @@ module \branch0 assign \rst_r $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" cell $or $60 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58800,11 +58800,11 @@ module \branch0 assign \reset_w $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 4 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" cell $or $62 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -58825,16 +58825,16 @@ module \branch0 assign \rok_l_s_rdok \issue_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_branch0_n_valid_o connect \B \busy_o connect \Y $63 end @@ -58913,9 +58913,9 @@ module \branch0 sync posedge \clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58931,9 +58931,9 @@ module \branch0 assign \req_l_s_req $65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" cell $or $68 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -58949,73 +58949,6 @@ module \branch0 assign \req_l_r_req $67 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__lk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__lk$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn$next - process $group_25 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__lk$next \oper_l__lk - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \oper_l__insn$next \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__lk 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__lk \oper_l__lk$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__insn \oper_l__insn$next - end attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -59113,7 +59046,45 @@ module \branch0 wire width 1 \oper_r__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 \oper_r__insn - process $group_32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 116 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $70 + parameter \WIDTH 116 + connect \A { \oper_l__insn \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + connect \S \issue_i + connect \Y $69 + end + process $group_25 assign \oper_r__insn_type 7'0000000 assign \oper_r__fn_unit 10'0000000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -59121,45 +59092,102 @@ module \branch0 assign \oper_r__lk 1'0 assign \oper_r__is_32bit 1'0 assign \oper_r__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69 + sync init + end + process $group_32 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm + assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok + assign \oper_l__lk$next \oper_l__lk + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__insn$next \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__insn \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + assign { \oper_l__insn$next \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_l__imm_data__imm_ok$next 1'0 end sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 10'0000000000 + update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_l__imm_data__imm_ok 1'0 + update \oper_l__lk 1'0 + update \oper_l__is_32bit 1'0 + update \oper_l__insn 32'00000000000000000000000000000000 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__imm_data__imm \oper_l__imm_data__imm$next + update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next + update \oper_l__lk \oper_l__lk$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__insn \oper_l__insn$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r0__spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r0__spr1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__spr1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $74 + parameter \WIDTH 65 + connect \A { \data_r0_l__spr1_ok \data_r0_l__spr1 } + connect \B { \spr1_ok \spr1 } + connect \S $72 + connect \Y $71 + end + process $group_39 + assign \data_r0__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__spr1_ok 1'0 + assign { \data_r0__spr1_ok \data_r0__spr1 } $71 + sync init + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $69 + wire width 1 $75 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $70 + cell $reduce_bool $76 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $69 + connect \Y $75 end - process $group_39 + process $group_41 assign \data_r0_l__spr1$next \data_r0_l__spr1 assign \data_r0_l__spr1_ok$next \data_r0_l__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r0_l__spr1_ok$next \data_r0_l__spr1$next } { \spr1_ok \spr1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -59173,62 +59201,62 @@ module \branch0 update \data_r0_l__spr1 \data_r0_l__spr1$next update \data_r0_l__spr1_ok \data_r0_l__spr1_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r0__spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r0__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r1__spr2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r1__spr2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r1_l__spr2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r1_l__spr2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__spr2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__spr2_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $79 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $71 + connect \Y $78 end - process $group_41 - assign \data_r0__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__spr1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r0__spr1_ok \data_r0__spr1 } { \spr1_ok \spr1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r0__spr1_ok \data_r0__spr1 } { \data_r0_l__spr1_ok \data_r0_l__spr1 } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 65 + connect \A { \data_r1_l__spr2_ok \data_r1_l__spr2 } + connect \B { \spr2_ok \spr2 } + connect \S $78 + connect \Y $77 + end + process $group_43 + assign \data_r1__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r1__spr2_ok 1'0 + assign { \data_r1__spr2_ok \data_r1__spr2 } $77 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r1_l__spr2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r1_l__spr2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__spr2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__spr2_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $73 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $74 + cell $reduce_bool $82 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $73 + connect \Y $81 end - process $group_43 + process $group_45 assign \data_r1_l__spr2$next \data_r1_l__spr2 assign \data_r1_l__spr2_ok$next \data_r1_l__spr2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r1_l__spr2_ok$next \data_r1_l__spr2$next } { \spr2_ok \spr2 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -59242,62 +59270,62 @@ module \branch0 update \data_r1_l__spr2 \data_r1_l__spr2$next update \data_r1_l__spr2_ok \data_r1_l__spr2_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r1__spr2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r1__spr2_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r2__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r2__nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r2_l__nia + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r2_l__nia$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $85 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $75 + connect \Y $84 end - process $group_45 - assign \data_r1__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r1__spr2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r1__spr2_ok \data_r1__spr2 } { \spr2_ok \spr2 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r1__spr2_ok \data_r1__spr2 } { \data_r1_l__spr2_ok \data_r1_l__spr2 } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 65 + connect \A { \data_r2_l__nia_ok \data_r2_l__nia } + connect \B { \nia_ok \nia } + connect \S $84 + connect \Y $83 + end + process $group_47 + assign \data_r2__nia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r2__nia_ok 1'0 + assign { \data_r2__nia_ok \data_r2__nia } $83 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r2_l__nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r2_l__nia$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__nia_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $77 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $78 + cell $reduce_bool $88 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $77 + connect \Y $87 end - process $group_47 + process $group_49 assign \data_r2_l__nia$next \data_r2_l__nia assign \data_r2_l__nia_ok$next \data_r2_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r2_l__nia_ok$next \data_r2_l__nia$next } { \nia_ok \nia } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -59311,233 +59339,205 @@ module \branch0 update \data_r2_l__nia \data_r2_l__nia$next update \data_r2_l__nia_ok \data_r2_l__nia_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r2__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r2__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $79 - end - process $group_49 - assign \data_r2__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r2__nia_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r2__nia_ok \data_r2__nia } { \nia_ok \nia } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r2__nia_ok \data_r2__nia } { \data_r2_l__nia_ok \data_r2_l__nia } - end - sync init - end process $group_51 assign \wrmask 3'000 assign \wrmask { \data_r2__nia_ok \data_r1__spr2_ok \data_r0__spr1_ok } sync init end process $group_52 - assign \alu_op__insn_type 7'0000000 - assign \alu_op__fn_unit 10'0000000000 - assign \alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok 1'0 - assign \alu_op__lk 1'0 - assign \alu_op__is_32bit 1'0 - assign \alu_op__insn 32'00000000000000000000000000000000 - assign { \alu_op__insn \alu_op__is_32bit \alu_op__lk { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + assign \alu_branch0_op__insn_type 7'0000000 + assign \alu_branch0_op__fn_unit 10'0000000000 + assign \alu_branch0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_op__imm_data__imm_ok 1'0 + assign \alu_branch0_op__lk 1'0 + assign \alu_branch0_op__is_32bit 1'0 + assign \alu_branch0_op__insn 32'00000000000000000000000000000000 + assign { \alu_branch0_op__insn \alu_branch0_op__is_32bit \alu_branch0_op__lk { \alu_branch0_op__imm_data__imm_ok \alu_branch0_op__imm_data__imm } \alu_branch0_op__fn_unit \alu_branch0_op__insn_type } { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - cell $mux $82 + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $90 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \oper_r__imm_data__imm_ok - connect \Y $81 + connect \Y $89 end process $group_59 assign \src_sel 1'0 - assign \src_sel $81 + assign \src_sel $89 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $92 parameter \WIDTH 64 connect \A \src2_i connect \B \oper_r__imm_data__imm connect \S \oper_r__imm_data__imm_ok - connect \Y $83 + connect \Y $91 end process $group_60 assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $83 + assign \src_or_imm $91 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $94 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $93 + end process $group_61 + assign \alu_branch0_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_spr1 $93 + sync init + end + process $group_62 assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r0$next \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r0 \src_r0$next end - process $group_62 - assign \alu_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_spr1 \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_spr1 \src_r0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $96 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $95 + end process $group_63 + assign \alu_branch0_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_spr2 $95 + sync init + end + process $group_64 assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r1$next \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r1 \src_r1$next end - process $group_64 - assign \alu_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_spr2 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_spr2 \src_r1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 4 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $98 + parameter \WIDTH 4 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $97 + end process $group_65 + assign \alu_branch0_cr_a 4'0000 + assign \alu_branch0_cr_a $97 + sync init + end + process $group_66 assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r2$next \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r2 4'0000 sync posedge \clk update \src_r2 \src_r2$next end - process $group_66 - assign \alu_cr_a 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_cr_a \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_cr_a \src_r2 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $100 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $99 + end process $group_67 + assign \alu_branch0_cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_cia $99 + sync init + end + process $group_68 assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r3$next \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r3 \src_r3$next end - process $group_68 - assign \alu_cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_cia \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_cia \src_r3 - end - sync init - end process $group_69 - assign \alu_p_valid_i 1'0 - assign \alu_p_valid_i \alui_l_q_alui + assign \alu_branch0_p_valid_i 1'0 + assign \alu_branch0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - cell $and $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + cell $and $102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_p_ready_o + connect \A \alu_branch0_p_ready_o connect \B \alui_l_q_alui - connect \Y $85 + connect \Y $101 end process $group_70 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $85 + assign \alui_l_r_alui$next $101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -59554,26 +59554,26 @@ module \branch0 sync init end process $group_72 - assign \alu_n_ready_i 1'0 - assign \alu_n_ready_i \alu_l_q_alu + assign \alu_branch0_n_ready_i 1'0 + assign \alu_branch0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + cell $and $104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_branch0_n_valid_o connect \B \alu_l_q_alu - connect \Y $87 + connect \Y $103 end process $group_73 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $87 + assign \alu_l_r_alu$next $103 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -59594,10 +59594,10 @@ module \branch0 assign \busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $106 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -59605,63 +59605,63 @@ module \branch0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \busy_o \busy_o \busy_o \busy_o } - connect \Y $89 + connect \Y $105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - cell $not $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \oper_r__imm_data__imm_ok - connect \Y $91 + connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $110 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $89 - connect \B { 1'1 1'1 $91 1'1 } - connect \Y $93 + connect \A $105 + connect \B { 1'1 1'1 $107 1'1 } + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $not $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $not $112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \rdmaskn - connect \Y $95 + connect \Y $111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $114 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $93 - connect \B $95 - connect \Y $97 + connect \A $109 + connect \B $111 + connect \Y $113 end process $group_76 assign \rd__rel 4'0000 - assign \rd__rel $97 + assign \rd__rel $113 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -59669,12 +59669,12 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $99 + connect \Y $115 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -59682,12 +59682,12 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $101 + connect \Y $117 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -59695,44 +59695,44 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $103 + connect \Y $119 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $122 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req - connect \B { $99 $101 $103 } - connect \Y $105 + connect \B { $115 $117 $119 } + connect \Y $121 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $105 + connect \A $121 connect \B \wrmask - connect \Y $107 + connect \Y $123 end process $group_77 assign \wr__rel 3'000 - assign \wr__rel $107 + assign \wr__rel $123 sync init end process $group_78 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest1_o { \data_r0__spr1_ok \data_r0__spr1 } [63:0] end @@ -59742,9 +59742,9 @@ module \branch0 wire width 64 \dest2_o process $group_79 assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest2_o { \data_r1__spr2_ok \data_r1__spr2 } [63:0] end @@ -59754,9 +59754,9 @@ module \branch0 wire width 64 \dest3_o process $group_80 assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest3_o { \data_r2__nia_ok \data_r2__nia } [63:0] end @@ -59764,8 +59764,8 @@ module \branch0 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.p" -module \p$32 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p" +module \p$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -59792,8 +59792,8 @@ module \p$32 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.n" -module \n$33 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" +module \n$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -59820,8 +59820,8 @@ module \n$33 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe.p" -module \p$35 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p" +module \p$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -59848,8 +59848,8 @@ module \p$35 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe.n" -module \n$36 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" +module \n$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -59876,8 +59876,8 @@ module \n$36 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe.main" -module \main$37 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" +module \main$34 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -60773,8 +60773,8 @@ module \main$37 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe" -module \pipe$34 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" +module \pipe$31 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -61047,11 +61047,11 @@ module \pipe$34 wire width 1 output 35 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \msr_ok$next - cell \p$35 \p + cell \p$32 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$36 \n + cell \n$33 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -61281,7 +61281,7 @@ module \pipe$34 wire width 64 \main_msr$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_msr_ok - cell \main$37 \main + cell \main$34 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -61758,8 +61758,8 @@ module \pipe$34 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu" -module \alu$31 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" +module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -61899,11 +61899,11 @@ module \alu$31 wire width 1 input 26 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 27 \p_ready_o - cell \p$32 \p + cell \p$29 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$33 \n + cell \n$30 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -62141,7 +62141,7 @@ module \alu$31 wire width 64 \pipe_msr$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_msr_ok - cell \pipe$34 \pipe + cell \pipe$31 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -62392,24 +62392,24 @@ module \alu$31 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" -module \src_l$38 +module \src_l$35 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 3 \r_src + wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62417,9 +62417,9 @@ module \src_l$38 connect \A \r_src connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62430,9 +62430,9 @@ module \src_l$38 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62456,9 +62456,9 @@ module \src_l$38 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62466,9 +62466,9 @@ module \src_l$38 connect \A \r_src connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62479,9 +62479,9 @@ module \src_l$38 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62497,11 +62497,11 @@ module \src_l$38 assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62514,11 +62514,11 @@ module \src_l$38 assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 6 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -62537,24 +62537,24 @@ module \src_l$38 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" -module \opc_l$39 +module \opc_l$36 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_opc + wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62562,9 +62562,9 @@ module \opc_l$39 connect \A \r_opc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62575,9 +62575,9 @@ module \opc_l$39 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62601,9 +62601,9 @@ module \opc_l$39 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62611,9 +62611,9 @@ module \opc_l$39 connect \A \r_opc connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62624,9 +62624,9 @@ module \opc_l$39 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62642,11 +62642,11 @@ module \opc_l$39 assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62659,11 +62659,11 @@ module \opc_l$39 assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62682,24 +62682,24 @@ module \opc_l$39 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" -module \req_l$40 +module \req_l$37 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62707,9 +62707,9 @@ module \req_l$40 connect \A \r_req connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62720,9 +62720,9 @@ module \req_l$40 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62746,9 +62746,9 @@ module \req_l$40 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62756,9 +62756,9 @@ module \req_l$40 connect \A \r_req connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62769,9 +62769,9 @@ module \req_l$40 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62787,11 +62787,11 @@ module \req_l$40 assign \q_req $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62804,11 +62804,11 @@ module \req_l$40 assign \qn_req $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 5 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -62827,22 +62827,22 @@ module \req_l$40 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" -module \rst_l$41 +module \rst_l$38 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62850,9 +62850,9 @@ module \rst_l$41 connect \A \r_rst connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62863,9 +62863,9 @@ module \rst_l$41 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62889,11 +62889,11 @@ module \rst_l$41 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62901,9 +62901,9 @@ module \rst_l$41 connect \A \r_rst connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62914,9 +62914,9 @@ module \rst_l$41 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62932,11 +62932,11 @@ module \rst_l$41 assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62949,11 +62949,11 @@ module \rst_l$41 assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62972,24 +62972,24 @@ module \rst_l$41 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" -module \rok_l$42 +module \rok_l$39 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -62997,9 +62997,9 @@ module \rok_l$42 connect \A \r_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63010,9 +63010,9 @@ module \rok_l$42 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63036,9 +63036,9 @@ module \rok_l$42 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63046,9 +63046,9 @@ module \rok_l$42 connect \A \r_rdok connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63059,9 +63059,9 @@ module \rok_l$42 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63077,11 +63077,11 @@ module \rok_l$42 assign \q_rdok $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63094,11 +63094,11 @@ module \rok_l$42 assign \qn_rdok $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63117,24 +63117,24 @@ module \rok_l$42 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" -module \alui_l$43 +module \alui_l$40 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63142,9 +63142,9 @@ module \alui_l$43 connect \A \r_alui connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63155,9 +63155,9 @@ module \alui_l$43 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63181,9 +63181,9 @@ module \alui_l$43 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63191,9 +63191,9 @@ module \alui_l$43 connect \A \r_alui connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63204,9 +63204,9 @@ module \alui_l$43 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63222,11 +63222,11 @@ module \alui_l$43 assign \q_alui $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63239,11 +63239,11 @@ module \alui_l$43 assign \qn_alui $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63262,24 +63262,24 @@ module \alui_l$43 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" -module \alu_l$44 +module \alu_l$41 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63287,9 +63287,9 @@ module \alu_l$44 connect \A \r_alu connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63300,9 +63300,9 @@ module \alu_l$44 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63326,9 +63326,9 @@ module \alu_l$44 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63336,9 +63336,9 @@ module \alu_l$44 connect \A \r_alu connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63349,9 +63349,9 @@ module \alu_l$44 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63367,11 +63367,11 @@ module \alu_l$44 assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63384,11 +63384,11 @@ module \alu_l$44 assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63560,9 +63560,9 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" wire width 64 output 33 \dest1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" - wire width 1 \alu_n_valid_o + wire width 1 \alu_trap0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" - wire width 1 \alu_n_ready_i + wire width 1 \alu_trap0_n_ready_i attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -63636,7 +63636,7 @@ module \trap0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 7 \alu_op__insn_type + wire width 7 \alu_trap0_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -63649,32 +63649,32 @@ module \trap0 attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \alu_op__fn_unit + wire width 10 \alu_trap0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 32 \alu_op__insn + wire width 32 \alu_trap0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 1 \alu_op__is_32bit + wire width 1 \alu_trap0_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \alu_op__traptype + wire width 4 \alu_trap0_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 13 \alu_op__trapaddr + wire width 13 \alu_trap0_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_ra + wire width 64 \alu_trap0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_rb + wire width 64 \alu_trap0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_spr1 + wire width 64 \alu_trap0_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_spr2 + wire width 64 \alu_trap0_spr2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_cia + wire width 64 \alu_trap0_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_msr + wire width 64 \alu_trap0_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" - wire width 1 \alu_p_valid_i + wire width 1 \alu_trap0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" - wire width 1 \alu_p_ready_o - cell \alu$31 \alu + wire width 1 \alu_trap0_p_ready_o + cell \alu_trap0 \alu_trap0 connect \rst \rst connect \clk \clk connect \o_ok \o_ok @@ -63687,130 +63687,130 @@ module \trap0 connect \nia \nia connect \msr_ok \msr_ok connect \msr \msr - connect \n_valid_o \alu_n_valid_o - connect \n_ready_i \alu_n_ready_i - connect \op__insn_type \alu_op__insn_type - connect \op__fn_unit \alu_op__fn_unit - connect \op__insn \alu_op__insn - connect \op__is_32bit \alu_op__is_32bit - connect \op__traptype \alu_op__traptype - connect \op__trapaddr \alu_op__trapaddr - connect \ra \alu_ra - connect \rb \alu_rb - connect \spr1$1 \alu_spr1 - connect \spr2$2 \alu_spr2 - connect \cia \alu_cia - connect \msr$3 \alu_msr - connect \p_valid_i \alu_p_valid_i - connect \p_ready_o \alu_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + connect \n_valid_o \alu_trap0_n_valid_o + connect \n_ready_i \alu_trap0_n_ready_i + connect \op__insn_type \alu_trap0_op__insn_type + connect \op__fn_unit \alu_trap0_op__fn_unit + connect \op__insn \alu_trap0_op__insn + connect \op__is_32bit \alu_trap0_op__is_32bit + connect \op__traptype \alu_trap0_op__traptype + connect \op__trapaddr \alu_trap0_op__trapaddr + connect \ra \alu_trap0_ra + connect \rb \alu_trap0_rb + connect \spr1$1 \alu_trap0_spr1 + connect \spr2$2 \alu_trap0_spr2 + connect \cia \alu_trap0_cia + connect \msr$3 \alu_trap0_msr + connect \p_valid_i \alu_trap0_p_valid_i + connect \p_ready_o \alu_trap0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 6 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 6 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 6 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 \src_l_q_src - cell \src_l$38 \src_l + cell \src_l$35 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src connect \r_src \src_l_r_src connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$39 \opc_l + cell \opc_l$36 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc connect \r_opc \opc_l_r_opc connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 5 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 5 \req_l_r_req - cell \req_l$40 \req_l + cell \req_l$37 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req connect \s_req \req_l_s_req connect \r_req \req_l_r_req end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$41 \rst_l + cell \rst_l$38 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst connect \r_rst \rst_l_r_rst end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$42 \rok_l + cell \rok_l$39 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok connect \s_rdok \rok_l_s_rdok connect \r_rdok \rok_l_r_rdok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$43 \alui_l + cell \alui_l$40 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$44 \alu_l + cell \alu_l$41 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177" - wire width 1 \all_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63821,11 +63821,11 @@ module \trap0 connect \B \rok_l_q_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 6 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -63833,9 +63833,9 @@ module \trap0 connect \A \rd__rel connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 6 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $or $7 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -63846,7 +63846,7 @@ module \trap0 connect \B \rd__go connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $reduce_and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -63854,9 +63854,9 @@ module \trap0 connect \A $6 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63872,9 +63872,9 @@ module \trap0 assign \all_rd $9 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -63884,11 +63884,11 @@ module \trap0 sync posedge \clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184" wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $not $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63896,9 +63896,9 @@ module \trap0 connect \A \all_rd_dly connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $and $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63914,16 +63914,16 @@ module \trap0 assign \all_rd_pulse $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 \alu_done process $group_3 assign \alu_done 1'0 - assign \alu_done \alu_n_valid_o + assign \alu_done \alu_trap0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly$next process $group_4 assign \alu_done_dly$next \alu_done_dly @@ -63933,11 +63933,11 @@ module \trap0 sync posedge \clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $not $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63945,9 +63945,9 @@ module \trap0 connect \A \alu_done_dly connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $and $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -63963,20 +63963,20 @@ module \trap0 assign \alu_pulse $17 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire width 5 \alu_pulsem process $group_6 assign \alu_pulsem 5'00000 assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" wire width 5 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64002,15 +64002,15 @@ module \trap0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire width 1 \done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 5 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" wire width 5 \wrmask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64018,9 +64018,9 @@ module \trap0 connect \A \wrmask connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 5 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64031,7 +64031,7 @@ module \trap0 connect \B $23 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $reduce_bool $27 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64039,7 +64039,7 @@ module \trap0 connect \A $25 connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64047,9 +64047,9 @@ module \trap0 connect \A $22 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64065,11 +64065,11 @@ module \trap0 assign \done_o $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64077,9 +64077,9 @@ module \trap0 connect \A \wr__go connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $34 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64087,9 +64087,9 @@ module \trap0 connect \A \prev_wr_go connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64105,21 +64105,21 @@ module \trap0 assign \wr_any $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_ready_i + connect \A \alu_trap0_n_ready_i connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64130,9 +64130,9 @@ module \trap0 connect \B $37 connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 5 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64143,9 +64143,9 @@ module \trap0 connect \B \wrmask connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64156,9 +64156,9 @@ module \trap0 connect \B 1'0 connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64169,9 +64169,9 @@ module \trap0 connect \B $43 connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64182,9 +64182,9 @@ module \trap0 connect \B 1'0 connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64192,12 +64192,12 @@ module \trap0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $47 - connect \B \alu_n_ready_i + connect \B \alu_trap0_n_ready_i connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64205,12 +64205,12 @@ module \trap0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_n_valid_o + connect \B \alu_trap0_n_valid_o connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64224,19 +64224,19 @@ module \trap0 process $group_10 assign \req_done 1'0 assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" cell $or $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64252,11 +64252,11 @@ module \trap0 assign \reset $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" cell $or $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -64272,11 +64272,11 @@ module \trap0 assign \rst_r $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 5 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" cell $or $60 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64292,11 +64292,11 @@ module \trap0 assign \reset_w $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" wire width 6 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 6 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" cell $or $62 parameter \A_SIGNED 0 parameter \A_WIDTH 6 @@ -64317,16 +64317,16 @@ module \trap0 assign \rok_l_s_rdok \issue_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_trap0_n_valid_o connect \B \busy_o connect \Y $63 end @@ -64405,9 +64405,9 @@ module \trap0 sync posedge \clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" wire width 5 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64423,9 +64423,9 @@ module \trap0 assign \req_l_s_req $65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" wire width 5 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" cell $or $68 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -64441,60 +64441,6 @@ module \trap0 assign \req_l_r_req $67 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__traptype - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__traptype$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 13 \oper_l__trapaddr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 13 \oper_l__trapaddr$next - process $group_25 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__insn$next \oper_l__insn - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__traptype$next \oper_l__traptype - assign \oper_l__trapaddr$next \oper_l__trapaddr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 - update \oper_l__insn 32'00000000000000000000000000000000 - update \oper_l__is_32bit 1'0 - update \oper_l__traptype 4'0000 - update \oper_l__trapaddr 13'0000000000000 - sync posedge \clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__insn \oper_l__insn$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__traptype \oper_l__traptype$next - update \oper_l__trapaddr \oper_l__trapaddr$next - end attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -64590,52 +64536,134 @@ module \trap0 wire width 4 \oper_r__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \oper_r__trapaddr - process $group_31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__traptype + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__traptype$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 13 \oper_l__trapaddr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 13 \oper_l__trapaddr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 67 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $70 + parameter \WIDTH 67 + connect \A { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } + connect \S \issue_i + connect \Y $69 + end + process $group_25 assign \oper_r__insn_type 7'0000000 assign \oper_r__fn_unit 10'0000000000 assign \oper_r__insn 32'00000000000000000000000000000000 assign \oper_r__is_32bit 1'0 assign \oper_r__traptype 4'0000 assign \oper_r__trapaddr 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $69 + sync init + end + process $group_31 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__insn$next \oper_l__insn + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__traptype$next \oper_l__traptype + assign \oper_l__trapaddr$next \oper_l__trapaddr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } + assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } end sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 10'0000000000 + update \oper_l__insn 32'00000000000000000000000000000000 + update \oper_l__is_32bit 1'0 + update \oper_l__traptype 4'0000 + update \oper_l__trapaddr 13'0000000000000 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__insn \oper_l__insn$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__traptype \oper_l__traptype$next + update \oper_l__trapaddr \oper_l__trapaddr$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $74 + parameter \WIDTH 65 + connect \A { \data_r0_l__o_ok \data_r0_l__o } + connect \B { \o_ok \o } + connect \S $72 + connect \Y $71 + end + process $group_37 + assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__o_ok 1'0 + assign { \data_r0__o_ok \data_r0__o } $71 + sync init + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $69 + wire width 1 $75 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $70 + cell $reduce_bool $76 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $69 + connect \Y $75 end - process $group_37 + process $group_39 assign \data_r0_l__o$next \data_r0_l__o assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -64649,62 +64677,62 @@ module \trap0 update \data_r0_l__o \data_r0_l__o$next update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r1__spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r1__spr1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r1_l__spr1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r1_l__spr1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__spr1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $79 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $71 + connect \Y $78 end - process $group_39 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r0__o_ok \data_r0__o } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 65 + connect \A { \data_r1_l__spr1_ok \data_r1_l__spr1 } + connect \B { \spr1_ok \spr1 } + connect \S $78 + connect \Y $77 + end + process $group_41 + assign \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r1__spr1_ok 1'0 + assign { \data_r1__spr1_ok \data_r1__spr1 } $77 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r1_l__spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r1_l__spr1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__spr1_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $73 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $74 + cell $reduce_bool $82 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $73 + connect \Y $81 end - process $group_41 + process $group_43 assign \data_r1_l__spr1$next \data_r1_l__spr1 assign \data_r1_l__spr1_ok$next \data_r1_l__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \spr1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -64718,62 +64746,62 @@ module \trap0 update \data_r1_l__spr1 \data_r1_l__spr1$next update \data_r1_l__spr1_ok \data_r1_l__spr1_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r1__spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r1__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r2__spr2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r2__spr2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r2_l__spr2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r2_l__spr2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__spr2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__spr2_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $85 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $75 + connect \Y $84 end - process $group_43 - assign \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r1__spr1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r1__spr1_ok \data_r1__spr1 } { \spr1_ok \spr1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r1__spr1_ok \data_r1__spr1 } { \data_r1_l__spr1_ok \data_r1_l__spr1 } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 65 + connect \A { \data_r2_l__spr2_ok \data_r2_l__spr2 } + connect \B { \spr2_ok \spr2 } + connect \S $84 + connect \Y $83 + end + process $group_45 + assign \data_r2__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r2__spr2_ok 1'0 + assign { \data_r2__spr2_ok \data_r2__spr2 } $83 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r2_l__spr2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r2_l__spr2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__spr2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__spr2_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $77 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $78 + cell $reduce_bool $88 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $77 + connect \Y $87 end - process $group_45 + process $group_47 assign \data_r2_l__spr2$next \data_r2_l__spr2 assign \data_r2_l__spr2_ok$next \data_r2_l__spr2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r2_l__spr2_ok$next \data_r2_l__spr2$next } { \spr2_ok \spr2 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -64787,62 +64815,62 @@ module \trap0 update \data_r2_l__spr2 \data_r2_l__spr2$next update \data_r2_l__spr2_ok \data_r2_l__spr2_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r2__spr2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r2__spr2_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r3__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r3__nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r3_l__nia + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r3_l__nia$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $89 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $90 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $91 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $79 + connect \Y $90 end - process $group_47 - assign \data_r2__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r2__spr2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r2__spr2_ok \data_r2__spr2 } { \spr2_ok \spr2 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r2__spr2_ok \data_r2__spr2 } { \data_r2_l__spr2_ok \data_r2_l__spr2 } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $92 + parameter \WIDTH 65 + connect \A { \data_r3_l__nia_ok \data_r3_l__nia } + connect \B { \nia_ok \nia } + connect \S $90 + connect \Y $89 + end + process $group_49 + assign \data_r3__nia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r3__nia_ok 1'0 + assign { \data_r3__nia_ok \data_r3__nia } $89 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r3_l__nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r3_l__nia$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r3_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r3_l__nia_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $81 + wire width 1 $93 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $82 + cell $reduce_bool $94 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $81 + connect \Y $93 end - process $group_49 + process $group_51 assign \data_r3_l__nia$next \data_r3_l__nia assign \data_r3_l__nia_ok$next \data_r3_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r3_l__nia_ok$next \data_r3_l__nia$next } { \nia_ok \nia } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -64856,62 +64884,62 @@ module \trap0 update \data_r3_l__nia \data_r3_l__nia$next update \data_r3_l__nia_ok \data_r3_l__nia_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r3__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r3__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r4__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r4__msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r4_l__msr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r4_l__msr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $95 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $96 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $97 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $83 + connect \Y $96 end - process $group_51 - assign \data_r3__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r3__nia_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r3__nia_ok \data_r3__nia } { \nia_ok \nia } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r3__nia_ok \data_r3__nia } { \data_r3_l__nia_ok \data_r3_l__nia } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $98 + parameter \WIDTH 65 + connect \A { \data_r4_l__msr_ok \data_r4_l__msr } + connect \B { \msr_ok \msr } + connect \S $96 + connect \Y $95 + end + process $group_53 + assign \data_r4__msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r4__msr_ok 1'0 + assign { \data_r4__msr_ok \data_r4__msr } $95 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r4_l__msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \data_r4_l__msr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r4_l__msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r4_l__msr_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $85 + wire width 1 $99 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $86 + cell $reduce_bool $100 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $85 + connect \Y $99 end - process $group_53 + process $group_55 assign \data_r4_l__msr$next \data_r4_l__msr assign \data_r4_l__msr_ok$next \data_r4_l__msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $99 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r4_l__msr_ok$next \data_r4_l__msr$next } { \msr_ok \msr } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -64925,262 +64953,234 @@ module \trap0 update \data_r4_l__msr \data_r4_l__msr$next update \data_r4_l__msr_ok \data_r4_l__msr_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r4__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r4__msr_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $87 - end - process $group_55 - assign \data_r4__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r4__msr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r4__msr_ok \data_r4__msr } { \msr_ok \msr } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r4__msr_ok \data_r4__msr } { \data_r4_l__msr_ok \data_r4_l__msr } - end - sync init - end process $group_57 assign \wrmask 5'00000 assign \wrmask { \data_r4__msr_ok \data_r3__nia_ok \data_r2__spr2_ok \data_r1__spr1_ok \data_r0__o_ok } sync init end process $group_58 - assign \alu_op__insn_type 7'0000000 - assign \alu_op__fn_unit 10'0000000000 - assign \alu_op__insn 32'00000000000000000000000000000000 - assign \alu_op__is_32bit 1'0 - assign \alu_op__traptype 4'0000 - assign \alu_op__trapaddr 13'0000000000000 - assign { \alu_op__trapaddr \alu_op__traptype \alu_op__is_32bit \alu_op__insn \alu_op__fn_unit \alu_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } + assign \alu_trap0_op__insn_type 7'0000000 + assign \alu_trap0_op__fn_unit 10'0000000000 + assign \alu_trap0_op__insn 32'00000000000000000000000000000000 + assign \alu_trap0_op__is_32bit 1'0 + assign \alu_trap0_op__traptype 4'0000 + assign \alu_trap0_op__trapaddr 13'0000000000000 + assign { \alu_trap0_op__trapaddr \alu_trap0_op__traptype \alu_trap0_op__is_32bit \alu_trap0_op__insn \alu_trap0_op__fn_unit \alu_trap0_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $102 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $101 + end process $group_64 + assign \alu_trap0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_ra $101 + sync init + end + process $group_65 assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r0$next \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r0 \src_r0$next end - process $group_65 - assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_ra \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_ra \src_r0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $104 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $103 + end process $group_66 + assign \alu_trap0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_rb $103 + sync init + end + process $group_67 assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r1$next \src2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r1 \src_r1$next end - process $group_67 - assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_rb \src2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_rb \src_r1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $106 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $105 + end process $group_68 + assign \alu_trap0_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_spr1 $105 + sync init + end + process $group_69 assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r2$next \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r2 \src_r2$next end - process $group_69 - assign \alu_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_spr1 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_spr1 \src_r2 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $108 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $107 + end process $group_70 + assign \alu_trap0_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_spr2 $107 + sync init + end + process $group_71 assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r3$next \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r3 \src_r3$next end - process $group_71 - assign \alu_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_spr2 \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_spr2 \src_r3 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $110 + parameter \WIDTH 64 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $109 + end process $group_72 + assign \alu_trap0_cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_cia $109 + sync init + end + process $group_73 assign \src_r4$next \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r4$next \src5_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r4 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r4 \src_r4$next end - process $group_73 - assign \alu_cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_cia \src5_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_cia \src_r4 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r5$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $112 + parameter \WIDTH 64 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $111 + end process $group_74 + assign \alu_trap0_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_msr $111 + sync init + end + process $group_75 assign \src_r5$next \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r5$next \src6_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r5 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r5 \src_r5$next end - process $group_75 - assign \alu_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_msr \src6_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_msr \src_r5 - end - sync init - end process $group_76 - assign \alu_p_valid_i 1'0 - assign \alu_p_valid_i \alui_l_q_alui + assign \alu_trap0_p_valid_i 1'0 + assign \alu_trap0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - cell $and $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + cell $and $114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_p_ready_o + connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $89 + connect \Y $113 end process $group_77 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $89 + assign \alui_l_r_alui$next $113 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -65197,26 +65197,26 @@ module \trap0 sync init end process $group_79 - assign \alu_n_ready_i 1'0 - assign \alu_n_ready_i \alu_l_q_alu + assign \alu_trap0_n_ready_i 1'0 + assign \alu_trap0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + cell $and $116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $91 + connect \Y $115 end process $group_80 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $91 + assign \alu_l_r_alu$next $115 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -65237,10 +65237,10 @@ module \trap0 assign \busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $118 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -65248,53 +65248,53 @@ module \trap0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o } - connect \Y $93 + connect \Y $117 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 - connect \A $93 + connect \A $117 connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } - connect \Y $95 + connect \Y $119 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $not $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $not $122 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \rdmaskn - connect \Y $97 + connect \Y $121 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 6 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 6 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $124 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 - connect \A $95 - connect \B $97 - connect \Y $99 + connect \A $119 + connect \B $121 + connect \Y $123 end process $group_83 assign \rd__rel 6'000000 - assign \rd__rel $99 + assign \rd__rel $123 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65302,12 +65302,12 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $101 + connect \Y $125 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65315,12 +65315,12 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $103 + connect \Y $127 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65328,12 +65328,12 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $105 + connect \Y $129 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65341,12 +65341,12 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $107 + connect \Y $131 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65354,44 +65354,44 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $109 + connect \Y $133 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 5 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 5 $135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $136 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \req_l_q_req - connect \B { $101 $103 $105 $107 $109 } - connect \Y $111 + connect \B { $125 $127 $129 $131 $133 } + connect \Y $135 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 5 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 5 $137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $138 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $111 + connect \A $135 connect \B \wrmask - connect \Y $113 + connect \Y $137 end process $group_84 assign \wr__rel 5'00000 - assign \wr__rel $113 + assign \wr__rel $137 sync init end process $group_85 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] end @@ -65401,9 +65401,9 @@ module \trap0 wire width 64 \dest2_o process $group_86 assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0] end @@ -65413,9 +65413,9 @@ module \trap0 wire width 64 \dest3_o process $group_87 assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest3_o { \data_r2__spr2_ok \data_r2__spr2 } [63:0] end @@ -65425,9 +65425,9 @@ module \trap0 wire width 64 \dest4_o process $group_88 assign \dest4_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest4_o { \data_r3__nia_ok \data_r3__nia } [63:0] end @@ -65437,9 +65437,9 @@ module \trap0 wire width 64 \dest5_o process $group_89 assign \dest5_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest5_o { \data_r4__msr_ok \data_r4__msr } [63:0] end @@ -65447,8 +65447,8 @@ module \trap0 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.p" -module \p$46 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p" +module \p$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -65475,8 +65475,8 @@ module \p$46 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.n" -module \n$47 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n" +module \n$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -65503,8 +65503,8 @@ module \n$47 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.p" -module \p$49 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.p" +module \p$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -65531,8 +65531,8 @@ module \p$49 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.n" -module \n$50 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.n" +module \n$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -65559,8 +65559,8 @@ module \n$50 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.input" -module \input$51 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.input" +module \input$47 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -65893,7 +65893,7 @@ module \input$51 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main.bpermd" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main.bpermd" module \bpermd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 input 0 \rs @@ -67610,7 +67610,7 @@ module \bpermd end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main.popcount" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main.popcount" module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" wire width 64 input 0 \a @@ -69229,7 +69229,7 @@ module \popcount end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main.clz" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main.clz" module \clz attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" wire width 64 input 0 \sig_in @@ -71871,8 +71871,8 @@ module \clz end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main" -module \main$52 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main" +module \main$48 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -73669,8 +73669,8 @@ module \main$52 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.output" -module \output$53 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.output" +module \output$49 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -74235,8 +74235,8 @@ module \output$53 connect \so 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe" -module \pipe$48 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe" +module \pipe$44 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -74577,11 +74577,11 @@ module \pipe$48 wire width 1 output 55 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \xer_ca_ok$next - cell \p$49 \p + cell \p$45 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$50 \n + cell \n$46 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -74851,7 +74851,7 @@ module \pipe$48 wire width 64 \input_ra$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \input_rb$44 - cell \input$51 \input + cell \input$47 \input connect \muxid \input_muxid connect \op__insn_type \input_op__insn_type connect \op__fn_unit \input_op__fn_unit @@ -75165,7 +75165,7 @@ module \pipe$48 wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_o_ok - cell \main$52 \main + cell \main$48 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -75491,7 +75491,7 @@ module \pipe$48 wire width 2 \output_xer_ca$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \output_xer_ca_ok - cell \output$53 \output + cell \output$49 \output connect \muxid \output_muxid connect \op__insn_type \output_op__insn_type connect \op__fn_unit \output_op__fn_unit @@ -76119,8 +76119,8 @@ module \pipe$48 connect \xer_ca_ok$96 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu" -module \alu$45 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" +module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -76276,11 +76276,11 @@ module \alu$45 wire width 1 input 32 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 33 \p_ready_o - cell \p$46 \p + cell \p$42 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$47 \n + cell \n$43 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -76566,7 +76566,7 @@ module \alu$45 wire width 2 \pipe_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_xer_ca_ok - cell \pipe$48 \pipe + cell \pipe$44 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -76865,24 +76865,24 @@ module \alu$45 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" -module \src_l$54 +module \src_l$50 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 2 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 input 3 \r_src + wire width 2 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 2 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -76890,9 +76890,9 @@ module \src_l$54 connect \A \r_src connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 2 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -76903,9 +76903,9 @@ module \src_l$54 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 2 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -76929,9 +76929,9 @@ module \src_l$54 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 2 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -76939,9 +76939,9 @@ module \src_l$54 connect \A \r_src connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 2 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -76952,9 +76952,9 @@ module \src_l$54 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 2 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -76970,11 +76970,11 @@ module \src_l$54 assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 2 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -76987,11 +76987,11 @@ module \src_l$54 assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 2 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 2 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -77010,24 +77010,24 @@ module \src_l$54 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" -module \opc_l$55 +module \opc_l$51 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_opc + wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77035,9 +77035,9 @@ module \opc_l$55 connect \A \r_opc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77048,9 +77048,9 @@ module \opc_l$55 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77074,9 +77074,9 @@ module \opc_l$55 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77084,9 +77084,9 @@ module \opc_l$55 connect \A \r_opc connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77097,9 +77097,9 @@ module \opc_l$55 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77115,11 +77115,11 @@ module \opc_l$55 assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77132,11 +77132,11 @@ module \opc_l$55 assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77155,24 +77155,24 @@ module \opc_l$55 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" -module \req_l$56 +module \req_l$52 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77180,9 +77180,9 @@ module \req_l$56 connect \A \r_req connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77193,9 +77193,9 @@ module \req_l$56 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77219,9 +77219,9 @@ module \req_l$56 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77229,9 +77229,9 @@ module \req_l$56 connect \A \r_req connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77242,9 +77242,9 @@ module \req_l$56 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77260,11 +77260,11 @@ module \req_l$56 assign \q_req $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77277,11 +77277,11 @@ module \req_l$56 assign \qn_req $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -77300,22 +77300,22 @@ module \req_l$56 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" -module \rst_l$57 +module \rst_l$53 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77323,9 +77323,9 @@ module \rst_l$57 connect \A \r_rst connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77336,9 +77336,9 @@ module \rst_l$57 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77362,11 +77362,11 @@ module \rst_l$57 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77374,9 +77374,9 @@ module \rst_l$57 connect \A \r_rst connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77387,9 +77387,9 @@ module \rst_l$57 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77405,11 +77405,11 @@ module \rst_l$57 assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77422,11 +77422,11 @@ module \rst_l$57 assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77445,24 +77445,24 @@ module \rst_l$57 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" -module \rok_l$58 +module \rok_l$54 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77470,9 +77470,9 @@ module \rok_l$58 connect \A \r_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77483,9 +77483,9 @@ module \rok_l$58 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77509,9 +77509,9 @@ module \rok_l$58 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77519,9 +77519,9 @@ module \rok_l$58 connect \A \r_rdok connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77532,9 +77532,9 @@ module \rok_l$58 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77550,11 +77550,11 @@ module \rok_l$58 assign \q_rdok $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77567,11 +77567,11 @@ module \rok_l$58 assign \qn_rdok $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77590,24 +77590,24 @@ module \rok_l$58 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" -module \alui_l$59 +module \alui_l$55 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77615,9 +77615,9 @@ module \alui_l$59 connect \A \r_alui connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77628,9 +77628,9 @@ module \alui_l$59 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77654,9 +77654,9 @@ module \alui_l$59 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77664,9 +77664,9 @@ module \alui_l$59 connect \A \r_alui connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77677,9 +77677,9 @@ module \alui_l$59 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77695,11 +77695,11 @@ module \alui_l$59 assign \q_alui $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77712,11 +77712,11 @@ module \alui_l$59 assign \qn_alui $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77735,24 +77735,24 @@ module \alui_l$59 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" -module \alu_l$60 +module \alu_l$56 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77760,9 +77760,9 @@ module \alu_l$60 connect \A \r_alu connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77773,9 +77773,9 @@ module \alu_l$60 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77799,9 +77799,9 @@ module \alu_l$60 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77809,9 +77809,9 @@ module \alu_l$60 connect \A \r_alu connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77822,9 +77822,9 @@ module \alu_l$60 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77840,11 +77840,11 @@ module \alu_l$60 assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -77857,11 +77857,11 @@ module \alu_l$60 assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78049,9 +78049,9 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" wire width 64 output 39 \dest1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" - wire width 1 \alu_n_valid_o + wire width 1 \alu_logical0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" - wire width 1 \alu_n_ready_i + wire width 1 \alu_logical0_n_ready_i attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -78125,7 +78125,7 @@ module \logical0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 7 \alu_op__insn_type + wire width 7 \alu_logical0_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -78138,56 +78138,56 @@ module \logical0 attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \alu_op__fn_unit + wire width 10 \alu_logical0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 \alu_op__imm_data__imm + wire width 64 \alu_logical0_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__imm_data__imm_ok + wire width 1 \alu_logical0_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__lk + wire width 1 \alu_logical0_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__rc__rc + wire width 1 \alu_logical0_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__rc__rc_ok + wire width 1 \alu_logical0_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__oe__oe + wire width 1 \alu_logical0_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__oe__oe_ok + wire width 1 \alu_logical0_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__invert_a + wire width 1 \alu_logical0_op__invert_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__zero_a + wire width 1 \alu_logical0_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 \alu_op__input_carry + wire width 2 \alu_logical0_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__invert_out + wire width 1 \alu_logical0_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 \alu_op__write_cr__data + wire width 3 \alu_logical0_op__write_cr__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__write_cr__ok + wire width 1 \alu_logical0_op__write_cr__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__output_carry + wire width 1 \alu_logical0_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__is_32bit + wire width 1 \alu_logical0_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_op__is_signed + wire width 1 \alu_logical0_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 \alu_op__data_len + wire width 4 \alu_logical0_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 32 \alu_op__insn + wire width 32 \alu_logical0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_ra + wire width 64 \alu_logical0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_rb + wire width 64 \alu_logical0_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" - wire width 1 \alu_p_valid_i + wire width 1 \alu_logical0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" - wire width 1 \alu_p_ready_o - cell \alu$45 \alu + wire width 1 \alu_logical0_p_ready_o + cell \alu_logical0 \alu_logical0 connect \rst \rst connect \clk \clk connect \o_ok \o_ok @@ -78196,140 +78196,140 @@ module \logical0 connect \cr_a \cr_a connect \xer_ca_ok \xer_ca_ok connect \xer_ca \xer_ca - connect \n_valid_o \alu_n_valid_o - connect \n_ready_i \alu_n_ready_i - connect \op__insn_type \alu_op__insn_type - connect \op__fn_unit \alu_op__fn_unit - connect \op__imm_data__imm \alu_op__imm_data__imm - connect \op__imm_data__imm_ok \alu_op__imm_data__imm_ok - connect \op__lk \alu_op__lk - connect \op__rc__rc \alu_op__rc__rc - connect \op__rc__rc_ok \alu_op__rc__rc_ok - connect \op__oe__oe \alu_op__oe__oe - connect \op__oe__oe_ok \alu_op__oe__oe_ok - connect \op__invert_a \alu_op__invert_a - connect \op__zero_a \alu_op__zero_a - connect \op__input_carry \alu_op__input_carry - connect \op__invert_out \alu_op__invert_out - connect \op__write_cr__data \alu_op__write_cr__data - connect \op__write_cr__ok \alu_op__write_cr__ok - connect \op__output_carry \alu_op__output_carry - connect \op__is_32bit \alu_op__is_32bit - connect \op__is_signed \alu_op__is_signed - connect \op__data_len \alu_op__data_len - connect \op__insn \alu_op__insn - connect \ra \alu_ra - connect \rb \alu_rb - connect \p_valid_i \alu_p_valid_i - connect \p_ready_o \alu_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + connect \n_valid_o \alu_logical0_n_valid_o + connect \n_ready_i \alu_logical0_n_ready_i + connect \op__insn_type \alu_logical0_op__insn_type + connect \op__fn_unit \alu_logical0_op__fn_unit + connect \op__imm_data__imm \alu_logical0_op__imm_data__imm + connect \op__imm_data__imm_ok \alu_logical0_op__imm_data__imm_ok + connect \op__lk \alu_logical0_op__lk + connect \op__rc__rc \alu_logical0_op__rc__rc + connect \op__rc__rc_ok \alu_logical0_op__rc__rc_ok + connect \op__oe__oe \alu_logical0_op__oe__oe + connect \op__oe__oe_ok \alu_logical0_op__oe__oe_ok + connect \op__invert_a \alu_logical0_op__invert_a + connect \op__zero_a \alu_logical0_op__zero_a + connect \op__input_carry \alu_logical0_op__input_carry + connect \op__invert_out \alu_logical0_op__invert_out + connect \op__write_cr__data \alu_logical0_op__write_cr__data + connect \op__write_cr__ok \alu_logical0_op__write_cr__ok + connect \op__output_carry \alu_logical0_op__output_carry + connect \op__is_32bit \alu_logical0_op__is_32bit + connect \op__is_signed \alu_logical0_op__is_signed + connect \op__data_len \alu_logical0_op__data_len + connect \op__insn \alu_logical0_op__insn + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \p_valid_i \alu_logical0_p_valid_i + connect \p_ready_o \alu_logical0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 2 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 2 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 2 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 2 \src_l_q_src - cell \src_l$54 \src_l + cell \src_l$50 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src connect \r_src \src_l_r_src connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$55 \opc_l + cell \opc_l$51 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc connect \r_opc \opc_l_r_opc connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req - cell \req_l$56 \req_l + cell \req_l$52 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req connect \s_req \req_l_s_req connect \r_req \req_l_r_req end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$57 \rst_l + cell \rst_l$53 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst connect \r_rst \rst_l_r_rst end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$58 \rok_l + cell \rok_l$54 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok connect \s_rdok \rok_l_s_rdok connect \r_rdok \rok_l_r_rdok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$59 \alui_l + cell \alui_l$55 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$60 \alu_l + cell \alu_l$56 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177" - wire width 1 \all_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78340,11 +78340,11 @@ module \logical0 connect \B \rok_l_q_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 2 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -78352,9 +78352,9 @@ module \logical0 connect \A \rd__rel connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 2 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $or $7 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -78365,7 +78365,7 @@ module \logical0 connect \B \rd__go connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $reduce_and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -78373,9 +78373,9 @@ module \logical0 connect \A $6 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78391,9 +78391,9 @@ module \logical0 assign \all_rd $9 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -78403,11 +78403,11 @@ module \logical0 sync posedge \clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184" wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $not $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78415,9 +78415,9 @@ module \logical0 connect \A \all_rd_dly connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $and $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78433,16 +78433,16 @@ module \logical0 assign \all_rd_pulse $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 \alu_done process $group_3 assign \alu_done 1'0 - assign \alu_done \alu_n_valid_o + assign \alu_done \alu_logical0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly$next process $group_4 assign \alu_done_dly$next \alu_done_dly @@ -78452,11 +78452,11 @@ module \logical0 sync posedge \clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $not $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78464,9 +78464,9 @@ module \logical0 connect \A \alu_done_dly connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $and $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78482,20 +78482,20 @@ module \logical0 assign \alu_pulse $17 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire width 3 \alu_pulsem process $group_6 assign \alu_pulsem 3'000 assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" wire width 3 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78521,15 +78521,15 @@ module \logical0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire width 1 \done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" wire width 3 \wrmask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78537,9 +78537,9 @@ module \logical0 connect \A \wrmask connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78550,7 +78550,7 @@ module \logical0 connect \B $23 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $reduce_bool $27 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78558,7 +78558,7 @@ module \logical0 connect \A $25 connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78566,9 +78566,9 @@ module \logical0 connect \A $22 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78584,11 +78584,11 @@ module \logical0 assign \done_o $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78596,9 +78596,9 @@ module \logical0 connect \A \wr__go connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $34 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78606,9 +78606,9 @@ module \logical0 connect \A \prev_wr_go connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78624,21 +78624,21 @@ module \logical0 assign \wr_any $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_ready_i + connect \A \alu_logical0_n_ready_i connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78649,9 +78649,9 @@ module \logical0 connect \B $37 connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78662,9 +78662,9 @@ module \logical0 connect \B \wrmask connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78675,9 +78675,9 @@ module \logical0 connect \B 1'0 connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78688,9 +78688,9 @@ module \logical0 connect \B $43 connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78701,9 +78701,9 @@ module \logical0 connect \B 1'0 connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78711,12 +78711,12 @@ module \logical0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $47 - connect \B \alu_n_ready_i + connect \B \alu_logical0_n_ready_i connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78724,12 +78724,12 @@ module \logical0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_n_valid_o + connect \B \alu_logical0_n_valid_o connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78743,19 +78743,19 @@ module \logical0 process $group_10 assign \req_done 1'0 assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" cell $or $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78771,11 +78771,11 @@ module \logical0 assign \reset $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" cell $or $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -78791,11 +78791,11 @@ module \logical0 assign \rst_r $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" cell $or $60 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78811,11 +78811,11 @@ module \logical0 assign \reset_w $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" wire width 2 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 2 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" cell $or $62 parameter \A_SIGNED 0 parameter \A_WIDTH 2 @@ -78836,16 +78836,16 @@ module \logical0 assign \rok_l_s_rdok \issue_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_logical0_n_valid_o connect \B \busy_o connect \Y $63 end @@ -78924,9 +78924,9 @@ module \logical0 sync posedge \clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78942,9 +78942,9 @@ module \logical0 assign \req_l_s_req $65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" cell $or $68 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -78960,171 +78960,6 @@ module \logical0 assign \req_l_r_req $67 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__lk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__lk$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \oper_l__input_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \oper_l__input_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_out - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__invert_out$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 3 \oper_l__write_cr__data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 3 \oper_l__write_cr__data$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr__ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr__ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn$next - process $group_25 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__lk$next \oper_l__lk - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__invert_a$next \oper_l__invert_a - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__invert_out$next \oper_l__invert_out - assign \oper_l__write_cr__data$next \oper_l__write_cr__data - assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - assign \oper_l__write_cr__data$next 3'000 - assign \oper_l__write_cr__ok$next 1'0 - assign \oper_l__insn$next 32'00000000000000000000000000000000 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__lk 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__invert_a 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__input_carry 2'00 - update \oper_l__invert_out 1'0 - update \oper_l__write_cr__data 3'000 - update \oper_l__write_cr__ok 1'0 - update \oper_l__output_carry 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__lk \oper_l__lk$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__invert_a \oper_l__invert_a$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__invert_out \oper_l__invert_out$next - update \oper_l__write_cr__data \oper_l__write_cr__data$next - update \oper_l__write_cr__ok \oper_l__write_cr__ok$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next - update \oper_l__insn \oper_l__insn$next - end attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -79252,7 +79087,97 @@ module \logical0 wire width 4 \oper_r__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 32 \oper_r__insn - process $group_45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_out + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_out$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 135 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $70 + parameter \WIDTH 135 + connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + connect \S \issue_i + connect \Y $69 + end + process $group_25 assign \oper_r__insn_type 7'0000000 assign \oper_r__fn_unit 10'0000000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -79273,45 +79198,148 @@ module \logical0 assign \oper_r__is_signed 1'0 assign \oper_r__data_len 4'0000 assign \oper_r__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69 + sync init + end + process $group_45 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm + assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok + assign \oper_l__lk$next \oper_l__lk + assign \oper_l__rc__rc$next \oper_l__rc__rc + assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok + assign \oper_l__oe__oe$next \oper_l__oe__oe + assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok + assign \oper_l__invert_a$next \oper_l__invert_a + assign \oper_l__zero_a$next \oper_l__zero_a + assign \oper_l__input_carry$next \oper_l__input_carry + assign \oper_l__invert_out$next \oper_l__invert_out + assign \oper_l__write_cr__data$next \oper_l__write_cr__data + assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok + assign \oper_l__output_carry$next \oper_l__output_carry + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__is_signed$next \oper_l__is_signed + assign \oper_l__data_len$next \oper_l__data_len + assign \oper_l__insn$next \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_l__imm_data__imm_ok$next 1'0 + assign \oper_l__rc__rc$next 1'0 + assign \oper_l__rc__rc_ok$next 1'0 + assign \oper_l__oe__oe$next 1'0 + assign \oper_l__oe__oe_ok$next 1'0 + assign \oper_l__write_cr__data$next 3'000 + assign \oper_l__write_cr__ok$next 1'0 + assign \oper_l__insn$next 32'00000000000000000000000000000000 end sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 10'0000000000 + update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_l__imm_data__imm_ok 1'0 + update \oper_l__lk 1'0 + update \oper_l__rc__rc 1'0 + update \oper_l__rc__rc_ok 1'0 + update \oper_l__oe__oe 1'0 + update \oper_l__oe__oe_ok 1'0 + update \oper_l__invert_a 1'0 + update \oper_l__zero_a 1'0 + update \oper_l__input_carry 2'00 + update \oper_l__invert_out 1'0 + update \oper_l__write_cr__data 3'000 + update \oper_l__write_cr__ok 1'0 + update \oper_l__output_carry 1'0 + update \oper_l__is_32bit 1'0 + update \oper_l__is_signed 1'0 + update \oper_l__data_len 4'0000 + update \oper_l__insn 32'00000000000000000000000000000000 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__imm_data__imm \oper_l__imm_data__imm$next + update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next + update \oper_l__lk \oper_l__lk$next + update \oper_l__rc__rc \oper_l__rc__rc$next + update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next + update \oper_l__oe__oe \oper_l__oe__oe$next + update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next + update \oper_l__invert_a \oper_l__invert_a$next + update \oper_l__zero_a \oper_l__zero_a$next + update \oper_l__input_carry \oper_l__input_carry$next + update \oper_l__invert_out \oper_l__invert_out$next + update \oper_l__write_cr__data \oper_l__write_cr__data$next + update \oper_l__write_cr__ok \oper_l__write_cr__ok$next + update \oper_l__output_carry \oper_l__output_carry$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__is_signed \oper_l__is_signed$next + update \oper_l__data_len \oper_l__data_len$next + update \oper_l__insn \oper_l__insn$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $74 + parameter \WIDTH 65 + connect \A { \data_r0_l__o_ok \data_r0_l__o } + connect \B { \o_ok \o } + connect \S $72 + connect \Y $71 + end + process $group_65 + assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__o_ok 1'0 + assign { \data_r0__o_ok \data_r0__o } $71 + sync init + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $69 + wire width 1 $75 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $70 + cell $reduce_bool $76 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $69 + connect \Y $75 end - process $group_65 + process $group_67 assign \data_r0_l__o$next \data_r0_l__o assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -79325,62 +79353,62 @@ module \logical0 update \data_r0_l__o \data_r0_l__o$next update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 5 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $79 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $71 + connect \Y $78 end - process $group_67 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r0__o_ok \data_r0__o } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 5 + connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } + connect \B { \cr_a_ok \cr_a } + connect \S $78 + connect \Y $77 + end + process $group_69 + assign \data_r1__cr_a 4'0000 + assign \data_r1__cr_a_ok 1'0 + assign { \data_r1__cr_a_ok \data_r1__cr_a } $77 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $73 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $74 + cell $reduce_bool $82 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $73 + connect \Y $81 end - process $group_69 + process $group_71 assign \data_r1_l__cr_a$next \data_r1_l__cr_a assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -79394,62 +79422,62 @@ module \logical0 update \data_r1_l__cr_a \data_r1_l__cr_a$next update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 3 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $85 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $75 + connect \Y $84 end - process $group_71 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r1__cr_a_ok \data_r1__cr_a } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r1__cr_a_ok \data_r1__cr_a } { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 3 + connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } + connect \B { \xer_ca_ok \xer_ca } + connect \S $84 + connect \Y $83 + end + process $group_73 + assign \data_r2__xer_ca 2'00 + assign \data_r2__xer_ca_ok 1'0 + assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r2_l__xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r2_l__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $77 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $78 + cell $reduce_bool $88 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $77 + connect \Y $87 end - process $group_73 + process $group_75 assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -79463,216 +79491,188 @@ module \logical0 update \data_r2_l__xer_ca \data_r2_l__xer_ca$next update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $79 - end - process $group_75 - assign \data_r2__xer_ca 2'00 - assign \data_r2__xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \xer_ca_ok \xer_ca } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } - end - sync init - end process $group_77 assign \wrmask 3'000 assign \wrmask { \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok } sync init end process $group_78 - assign \alu_op__insn_type 7'0000000 - assign \alu_op__fn_unit 10'0000000000 - assign \alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok 1'0 - assign \alu_op__lk 1'0 - assign \alu_op__rc__rc 1'0 - assign \alu_op__rc__rc_ok 1'0 - assign \alu_op__oe__oe 1'0 - assign \alu_op__oe__oe_ok 1'0 - assign \alu_op__invert_a 1'0 - assign \alu_op__zero_a 1'0 - assign \alu_op__input_carry 2'00 - assign \alu_op__invert_out 1'0 - assign \alu_op__write_cr__data 3'000 - assign \alu_op__write_cr__ok 1'0 - assign \alu_op__output_carry 1'0 - assign \alu_op__is_32bit 1'0 - assign \alu_op__is_signed 1'0 - assign \alu_op__data_len 4'0000 - assign \alu_op__insn 32'00000000000000000000000000000000 - assign { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry { \alu_op__write_cr__ok \alu_op__write_cr__data } \alu_op__invert_out \alu_op__input_carry \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } \alu_op__lk { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + assign \alu_logical0_op__insn_type 7'0000000 + assign \alu_logical0_op__fn_unit 10'0000000000 + assign \alu_logical0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_op__imm_data__imm_ok 1'0 + assign \alu_logical0_op__lk 1'0 + assign \alu_logical0_op__rc__rc 1'0 + assign \alu_logical0_op__rc__rc_ok 1'0 + assign \alu_logical0_op__oe__oe 1'0 + assign \alu_logical0_op__oe__oe_ok 1'0 + assign \alu_logical0_op__invert_a 1'0 + assign \alu_logical0_op__zero_a 1'0 + assign \alu_logical0_op__input_carry 2'00 + assign \alu_logical0_op__invert_out 1'0 + assign \alu_logical0_op__write_cr__data 3'000 + assign \alu_logical0_op__write_cr__ok 1'0 + assign \alu_logical0_op__output_carry 1'0 + assign \alu_logical0_op__is_32bit 1'0 + assign \alu_logical0_op__is_signed 1'0 + assign \alu_logical0_op__data_len 4'0000 + assign \alu_logical0_op__insn 32'00000000000000000000000000000000 + assign { \alu_logical0_op__insn \alu_logical0_op__data_len \alu_logical0_op__is_signed \alu_logical0_op__is_32bit \alu_logical0_op__output_carry { \alu_logical0_op__write_cr__ok \alu_logical0_op__write_cr__data } \alu_logical0_op__invert_out \alu_logical0_op__input_carry \alu_logical0_op__zero_a \alu_logical0_op__invert_a { \alu_logical0_op__oe__oe_ok \alu_logical0_op__oe__oe } { \alu_logical0_op__rc__rc_ok \alu_logical0_op__rc__rc } \alu_logical0_op__lk { \alu_logical0_op__imm_data__imm_ok \alu_logical0_op__imm_data__imm } \alu_logical0_op__fn_unit \alu_logical0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 1 \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - cell $mux $82 + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $90 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \oper_r__zero_a - connect \Y $81 + connect \Y $89 end process $group_98 assign \src_sel 1'0 - assign \src_sel $81 + assign \src_sel $89 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $92 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $83 + connect \Y $91 end process $group_99 assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $83 + assign \src_or_imm $91 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 1 \src_sel$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - cell $mux $87 + wire width 1 \src_sel$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $95 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \oper_r__imm_data__imm_ok - connect \Y $86 + connect \Y $94 end process $group_100 - assign \src_sel$85 1'0 - assign \src_sel$85 $86 + assign \src_sel$93 1'0 + assign \src_sel$93 $94 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" - wire width 64 \src_or_imm$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 64 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" + wire width 64 \src_or_imm$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $98 parameter \WIDTH 64 connect \A \src2_i connect \B \oper_r__imm_data__imm connect \S \oper_r__imm_data__imm_ok - connect \Y $89 + connect \Y $97 end process $group_101 - assign \src_or_imm$88 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$88 $89 + assign \src_or_imm$96 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$96 $97 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $100 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $99 + end process $group_102 + assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_ra $99 + sync init + end + process $group_103 assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r0$next \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r0 \src_r0$next end - process $group_103 - assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_ra \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_ra \src_r0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $102 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$96 + connect \S \src_sel$93 + connect \Y $101 + end process $group_104 + assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_rb $101 + sync init + end + process $group_105 assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel$85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel$93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r1$next \src_or_imm$88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case + assign \src_r1$next \src_or_imm$96 end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r1 \src_r1$next end - process $group_105 - assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel$85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_rb \src_or_imm$88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_rb \src_r1 - end - sync init - end process $group_106 - assign \alu_p_valid_i 1'0 - assign \alu_p_valid_i \alui_l_q_alui + assign \alu_logical0_p_valid_i 1'0 + assign \alu_logical0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - cell $and $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + cell $and $104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_p_ready_o + connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $91 + connect \Y $103 end process $group_107 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $91 + assign \alui_l_r_alui$next $103 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -79689,26 +79689,26 @@ module \logical0 sync init end process $group_109 - assign \alu_n_ready_i 1'0 - assign \alu_n_ready_i \alu_l_q_alu + assign \alu_logical0_n_ready_i 1'0 + assign \alu_logical0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + cell $and $106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $93 + connect \Y $105 end process $group_110 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $93 + assign \alu_l_r_alu$next $105 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -79729,10 +79729,10 @@ module \logical0 assign \busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 2 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $108 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -79740,73 +79740,73 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \src_l_q_src connect \B { \busy_o \busy_o } - connect \Y $95 + connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - cell $not $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \oper_r__zero_a - connect \Y $97 + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - cell $not $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \oper_r__imm_data__imm_ok - connect \Y $99 + connect \Y $111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 2 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $114 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $95 - connect \B { $99 $97 } - connect \Y $101 + connect \A $107 + connect \B { $111 $109 } + connect \Y $113 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 2 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $not $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $not $116 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \rdmaskn - connect \Y $103 + connect \Y $115 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 2 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $118 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $101 - connect \B $103 - connect \Y $105 + connect \A $113 + connect \B $115 + connect \Y $117 end process $group_113 assign \rd__rel 2'00 - assign \rd__rel $105 + assign \rd__rel $117 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79814,12 +79814,12 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $107 + connect \Y $119 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79827,12 +79827,12 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $109 + connect \Y $121 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79840,44 +79840,44 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $111 + connect \Y $123 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req - connect \B { $107 $109 $111 } - connect \Y $113 + connect \B { $119 $121 $123 } + connect \Y $125 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $113 + connect \A $125 connect \B \wrmask - connect \Y $115 + connect \Y $127 end process $group_114 assign \wr__rel 3'000 - assign \wr__rel $115 + assign \wr__rel $127 sync init end process $group_115 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] end @@ -79887,9 +79887,9 @@ module \logical0 wire width 4 \dest2_o process $group_116 assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] end @@ -79899,9 +79899,9 @@ module \logical0 wire width 2 \dest3_o process $group_117 assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] end @@ -79909,8 +79909,8 @@ module \logical0 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.p" -module \p$62 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" +module \p$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -79937,8 +79937,8 @@ module \p$62 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.n" -module \n$63 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" +module \n$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -79965,8 +79965,8 @@ module \n$63 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.p" -module \p$65 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.p" +module \p$60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -79993,8 +79993,8 @@ module \p$65 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.n" -module \n$66 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.n" +module \n$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -80021,8 +80021,8 @@ module \n$66 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.input" -module \input$67 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input" +module \input$62 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -80354,7 +80354,7 @@ module \input$67 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.main.rotator.rotl" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator.rotl" module \rotl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" wire width 64 input 0 \a @@ -80438,7 +80438,7 @@ module \rotl end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.main.rotator" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator" module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:43" wire width 5 input 0 \me @@ -81189,8 +81189,8 @@ module \rotator end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.main" -module \main$68 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main" +module \main$63 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -81666,8 +81666,8 @@ module \main$68 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.output" -module \output$69 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output" +module \output$64 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -82189,8 +82189,8 @@ module \output$69 connect \so 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe" -module \pipe$64 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe" +module \pipe$59 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -82517,11 +82517,11 @@ module \pipe$64 wire width 1 output 51 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \xer_ca_ok$next - cell \p$65 \p + cell \p$60 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$66 \n + cell \n$61 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -82787,7 +82787,7 @@ module \pipe$64 wire width 64 \input_rc$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 2 \input_xer_ca$41 - cell \input$67 \input + cell \input$62 \input connect \muxid \input_muxid connect \op__insn_type \input_op__insn_type connect \op__fn_unit \input_op__fn_unit @@ -83091,7 +83091,7 @@ module \pipe$64 wire width 1 \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 2 \main_xer_ca - cell \main$68 \main + cell \main$63 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -83401,7 +83401,7 @@ module \pipe$64 wire width 2 \output_xer_ca$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \output_xer_ca_ok - cell \output$69 \output + cell \output$64 \output connect \muxid \output_muxid connect \op__insn_type \output_op__insn_type connect \op__fn_unit \output_op__fn_unit @@ -84015,8 +84015,8 @@ module \pipe$64 connect \xer_ca_ok$87 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu" -module \alu$61 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" +module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -84170,11 +84170,11 @@ module \alu$61 wire width 1 input 31 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 32 \p_ready_o - cell \p$62 \p + cell \p$57 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$63 \n + cell \n$58 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -84452,7 +84452,7 @@ module \alu$61 wire width 2 \pipe_xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_xer_ca_ok - cell \pipe$64 \pipe + cell \pipe$59 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -84745,24 +84745,24 @@ module \alu$61 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" -module \src_l$70 +module \src_l$65 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \r_src + wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84770,9 +84770,9 @@ module \src_l$70 connect \A \r_src connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84783,9 +84783,9 @@ module \src_l$70 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84809,9 +84809,9 @@ module \src_l$70 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84819,9 +84819,9 @@ module \src_l$70 connect \A \r_src connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84832,9 +84832,9 @@ module \src_l$70 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84850,11 +84850,11 @@ module \src_l$70 assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84867,11 +84867,11 @@ module \src_l$70 assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -84890,24 +84890,24 @@ module \src_l$70 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" -module \opc_l$71 +module \opc_l$66 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_opc + wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -84915,9 +84915,9 @@ module \opc_l$71 connect \A \r_opc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -84928,9 +84928,9 @@ module \opc_l$71 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -84954,9 +84954,9 @@ module \opc_l$71 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -84964,9 +84964,9 @@ module \opc_l$71 connect \A \r_opc connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -84977,9 +84977,9 @@ module \opc_l$71 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -84995,11 +84995,11 @@ module \opc_l$71 assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85012,11 +85012,11 @@ module \opc_l$71 assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85035,24 +85035,24 @@ module \opc_l$71 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" -module \req_l$72 +module \req_l$67 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85060,9 +85060,9 @@ module \req_l$72 connect \A \r_req connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85073,9 +85073,9 @@ module \req_l$72 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85099,9 +85099,9 @@ module \req_l$72 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85109,9 +85109,9 @@ module \req_l$72 connect \A \r_req connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85122,9 +85122,9 @@ module \req_l$72 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85140,11 +85140,11 @@ module \req_l$72 assign \q_req $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85157,11 +85157,11 @@ module \req_l$72 assign \qn_req $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -85180,22 +85180,22 @@ module \req_l$72 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" -module \rst_l$73 +module \rst_l$68 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85203,9 +85203,9 @@ module \rst_l$73 connect \A \r_rst connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85216,9 +85216,9 @@ module \rst_l$73 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85242,11 +85242,11 @@ module \rst_l$73 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85254,9 +85254,9 @@ module \rst_l$73 connect \A \r_rst connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85267,9 +85267,9 @@ module \rst_l$73 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85285,11 +85285,11 @@ module \rst_l$73 assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85302,11 +85302,11 @@ module \rst_l$73 assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85325,24 +85325,24 @@ module \rst_l$73 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" -module \rok_l$74 +module \rok_l$69 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85350,9 +85350,9 @@ module \rok_l$74 connect \A \r_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85363,9 +85363,9 @@ module \rok_l$74 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85389,9 +85389,9 @@ module \rok_l$74 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85399,9 +85399,9 @@ module \rok_l$74 connect \A \r_rdok connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85412,9 +85412,9 @@ module \rok_l$74 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85430,11 +85430,11 @@ module \rok_l$74 assign \q_rdok $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85447,11 +85447,11 @@ module \rok_l$74 assign \qn_rdok $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85470,24 +85470,24 @@ module \rok_l$74 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" -module \alui_l$75 +module \alui_l$70 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85495,9 +85495,9 @@ module \alui_l$75 connect \A \r_alui connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85508,9 +85508,9 @@ module \alui_l$75 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85534,9 +85534,9 @@ module \alui_l$75 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85544,9 +85544,9 @@ module \alui_l$75 connect \A \r_alui connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85557,9 +85557,9 @@ module \alui_l$75 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85575,11 +85575,11 @@ module \alui_l$75 assign \q_alui $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85592,11 +85592,11 @@ module \alui_l$75 assign \qn_alui $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85615,24 +85615,24 @@ module \alui_l$75 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" -module \alu_l$76 +module \alu_l$71 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85640,9 +85640,9 @@ module \alu_l$76 connect \A \r_alu connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85653,9 +85653,9 @@ module \alu_l$76 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85679,9 +85679,9 @@ module \alu_l$76 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85689,9 +85689,9 @@ module \alu_l$76 connect \A \r_alu connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85702,9 +85702,9 @@ module \alu_l$76 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85720,11 +85720,11 @@ module \alu_l$76 assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85737,11 +85737,11 @@ module \alu_l$76 assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -85927,9 +85927,9 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" wire width 64 output 38 \dest1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" - wire width 1 \alu_n_valid_o + wire width 1 \alu_shift_rot0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" - wire width 1 \alu_n_ready_i + wire width 1 \alu_shift_rot0_n_ready_i attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -86003,7 +86003,7 @@ module \shiftrot0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 7 \alu_op__insn_type + wire width 7 \alu_shift_rot0_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -86016,54 +86016,54 @@ module \shiftrot0 attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \alu_op__fn_unit + wire width 10 \alu_shift_rot0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 64 \alu_op__imm_data__imm + wire width 64 \alu_shift_rot0_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__imm_data__imm_ok + wire width 1 \alu_shift_rot0_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__rc__rc + wire width 1 \alu_shift_rot0_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__rc__rc_ok + wire width 1 \alu_shift_rot0_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__oe__oe + wire width 1 \alu_shift_rot0_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__oe__oe_ok + wire width 1 \alu_shift_rot0_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 3 \alu_op__write_cr__data + wire width 3 \alu_shift_rot0_op__write_cr__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__write_cr__ok + wire width 1 \alu_shift_rot0_op__write_cr__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 2 \alu_op__input_carry + wire width 2 \alu_shift_rot0_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__output_carry + wire width 1 \alu_shift_rot0_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__input_cr + wire width 1 \alu_shift_rot0_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__output_cr + wire width 1 \alu_shift_rot0_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__is_32bit + wire width 1 \alu_shift_rot0_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \alu_op__is_signed + wire width 1 \alu_shift_rot0_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 32 \alu_op__insn + wire width 32 \alu_shift_rot0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_ra + wire width 64 \alu_shift_rot0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_rb + wire width 64 \alu_shift_rot0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_rc + wire width 64 \alu_shift_rot0_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 2 \alu_xer_ca + wire width 2 \alu_shift_rot0_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" - wire width 1 \alu_p_valid_i + wire width 1 \alu_shift_rot0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" - wire width 1 \alu_p_ready_o - cell \alu$61 \alu + wire width 1 \alu_shift_rot0_p_ready_o + cell \alu_shift_rot0 \alu_shift_rot0 connect \rst \rst connect \clk \clk connect \o_ok \o_ok @@ -86072,139 +86072,139 @@ module \shiftrot0 connect \cr_a \cr_a connect \xer_ca_ok \xer_ca_ok connect \xer_ca \xer_ca - connect \n_valid_o \alu_n_valid_o - connect \n_ready_i \alu_n_ready_i - connect \op__insn_type \alu_op__insn_type - connect \op__fn_unit \alu_op__fn_unit - connect \op__imm_data__imm \alu_op__imm_data__imm - connect \op__imm_data__imm_ok \alu_op__imm_data__imm_ok - connect \op__rc__rc \alu_op__rc__rc - connect \op__rc__rc_ok \alu_op__rc__rc_ok - connect \op__oe__oe \alu_op__oe__oe - connect \op__oe__oe_ok \alu_op__oe__oe_ok - connect \op__write_cr__data \alu_op__write_cr__data - connect \op__write_cr__ok \alu_op__write_cr__ok - connect \op__input_carry \alu_op__input_carry - connect \op__output_carry \alu_op__output_carry - connect \op__input_cr \alu_op__input_cr - connect \op__output_cr \alu_op__output_cr - connect \op__is_32bit \alu_op__is_32bit - connect \op__is_signed \alu_op__is_signed - connect \op__insn \alu_op__insn - connect \ra \alu_ra - connect \rb \alu_rb - connect \rc \alu_rc - connect \xer_ca$1 \alu_xer_ca - connect \p_valid_i \alu_p_valid_i - connect \p_ready_o \alu_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + connect \n_valid_o \alu_shift_rot0_n_valid_o + connect \n_ready_i \alu_shift_rot0_n_ready_i + connect \op__insn_type \alu_shift_rot0_op__insn_type + connect \op__fn_unit \alu_shift_rot0_op__fn_unit + connect \op__imm_data__imm \alu_shift_rot0_op__imm_data__imm + connect \op__imm_data__imm_ok \alu_shift_rot0_op__imm_data__imm_ok + connect \op__rc__rc \alu_shift_rot0_op__rc__rc + connect \op__rc__rc_ok \alu_shift_rot0_op__rc__rc_ok + connect \op__oe__oe \alu_shift_rot0_op__oe__oe + connect \op__oe__oe_ok \alu_shift_rot0_op__oe__oe_ok + connect \op__write_cr__data \alu_shift_rot0_op__write_cr__data + connect \op__write_cr__ok \alu_shift_rot0_op__write_cr__ok + connect \op__input_carry \alu_shift_rot0_op__input_carry + connect \op__output_carry \alu_shift_rot0_op__output_carry + connect \op__input_cr \alu_shift_rot0_op__input_cr + connect \op__output_cr \alu_shift_rot0_op__output_cr + connect \op__is_32bit \alu_shift_rot0_op__is_32bit + connect \op__is_signed \alu_shift_rot0_op__is_signed + connect \op__insn \alu_shift_rot0_op__insn + connect \ra \alu_shift_rot0_ra + connect \rb \alu_shift_rot0_rb + connect \rc \alu_shift_rot0_rc + connect \xer_ca$1 \alu_shift_rot0_xer_ca + connect \p_valid_i \alu_shift_rot0_p_valid_i + connect \p_ready_o \alu_shift_rot0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 4 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src - cell \src_l$70 \src_l + cell \src_l$65 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src connect \r_src \src_l_r_src connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$71 \opc_l + cell \opc_l$66 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc connect \r_opc \opc_l_r_opc connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req - cell \req_l$72 \req_l + cell \req_l$67 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req connect \s_req \req_l_s_req connect \r_req \req_l_r_req end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$73 \rst_l + cell \rst_l$68 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst connect \r_rst \rst_l_r_rst end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$74 \rok_l + cell \rok_l$69 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok connect \s_rdok \rok_l_s_rdok connect \r_rdok \rok_l_r_rdok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$75 \alui_l + cell \alui_l$70 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$76 \alu_l + cell \alu_l$71 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177" - wire width 1 \all_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86215,11 +86215,11 @@ module \shiftrot0 connect \B \rok_l_q_rdok connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 4 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $not $5 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -86227,9 +86227,9 @@ module \shiftrot0 connect \A \rd__rel connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 4 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $or $7 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -86240,7 +86240,7 @@ module \shiftrot0 connect \B \rd__go connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $reduce_and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -86248,9 +86248,9 @@ module \shiftrot0 connect \A $6 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86266,9 +86266,9 @@ module \shiftrot0 assign \all_rd $9 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -86278,11 +86278,11 @@ module \shiftrot0 sync posedge \clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184" wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $not $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86290,9 +86290,9 @@ module \shiftrot0 connect \A \all_rd_dly connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" cell $and $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86308,16 +86308,16 @@ module \shiftrot0 assign \all_rd_pulse $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 1 \alu_done process $group_3 assign \alu_done 1'0 - assign \alu_done \alu_n_valid_o + assign \alu_done \alu_shift_rot0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" wire width 1 \alu_done_dly$next process $group_4 assign \alu_done_dly$next \alu_done_dly @@ -86327,11 +86327,11 @@ module \shiftrot0 sync posedge \clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $not $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86339,9 +86339,9 @@ module \shiftrot0 connect \A \alu_done_dly connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" cell $and $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86357,20 +86357,20 @@ module \shiftrot0 assign \alu_pulse $17 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire width 3 \alu_pulsem process $group_6 assign \alu_pulsem 3'000 assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" wire width 3 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86396,15 +86396,15 @@ module \shiftrot0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire width 1 \done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" wire width 3 \wrmask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86412,9 +86412,9 @@ module \shiftrot0 connect \A \wrmask connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86425,7 +86425,7 @@ module \shiftrot0 connect \B $23 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $reduce_bool $27 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86433,7 +86433,7 @@ module \shiftrot0 connect \A $25 connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86441,9 +86441,9 @@ module \shiftrot0 connect \A $22 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86459,11 +86459,11 @@ module \shiftrot0 assign \done_o $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86471,9 +86471,9 @@ module \shiftrot0 connect \A \wr__go connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $34 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86481,9 +86481,9 @@ module \shiftrot0 connect \A \prev_wr_go connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86499,21 +86499,21 @@ module \shiftrot0 assign \wr_any $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_ready_i + connect \A \alu_shift_rot0_n_ready_i connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86524,9 +86524,9 @@ module \shiftrot0 connect \B $37 connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86537,9 +86537,9 @@ module \shiftrot0 connect \B \wrmask connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86550,9 +86550,9 @@ module \shiftrot0 connect \B 1'0 connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86563,9 +86563,9 @@ module \shiftrot0 connect \B $43 connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86576,9 +86576,9 @@ module \shiftrot0 connect \B 1'0 connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86586,12 +86586,12 @@ module \shiftrot0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $47 - connect \B \alu_n_ready_i + connect \B \alu_shift_rot0_n_ready_i connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86599,12 +86599,12 @@ module \shiftrot0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_n_valid_o + connect \B \alu_shift_rot0_n_valid_o connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86618,19 +86618,19 @@ module \shiftrot0 process $group_10 assign \req_done 1'0 assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" cell $or $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86646,11 +86646,11 @@ module \shiftrot0 assign \reset $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" cell $or $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -86666,11 +86666,11 @@ module \shiftrot0 assign \rst_r $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" cell $or $60 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86686,11 +86686,11 @@ module \shiftrot0 assign \reset_w $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 4 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" cell $or $62 parameter \A_SIGNED 0 parameter \A_WIDTH 4 @@ -86711,16 +86711,16 @@ module \shiftrot0 assign \rok_l_s_rdok \issue_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_shift_rot0_n_valid_o connect \B \busy_o connect \Y $63 end @@ -86799,9 +86799,9 @@ module \shiftrot0 sync posedge \clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86817,9 +86817,9 @@ module \shiftrot0 assign \req_l_s_req $65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" cell $or $68 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -86835,150 +86835,6 @@ module \shiftrot0 assign \req_l_r_req $67 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 10 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 3 \oper_l__write_cr__data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 3 \oper_l__write_cr__data$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr__ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__write_cr__ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \oper_l__input_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \oper_l__input_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__input_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__input_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__output_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 32 \oper_l__insn$next - process $group_25 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__write_cr__data$next \oper_l__write_cr__data - assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__input_cr$next \oper_l__input_cr - assign \oper_l__output_cr$next \oper_l__output_cr - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - assign \oper_l__write_cr__data$next 3'000 - assign \oper_l__write_cr__ok$next 1'0 - assign \oper_l__insn$next 32'00000000000000000000000000000000 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__write_cr__data 3'000 - update \oper_l__write_cr__ok 1'0 - update \oper_l__input_carry 2'00 - update \oper_l__output_carry 1'0 - update \oper_l__input_cr 1'0 - update \oper_l__output_cr 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__write_cr__data \oper_l__write_cr__data$next - update \oper_l__write_cr__ok \oper_l__write_cr__ok$next - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__input_cr \oper_l__input_cr$next - update \oper_l__output_cr \oper_l__output_cr$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__insn \oper_l__insn$next - end attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -87100,7 +86956,85 @@ module \shiftrot0 wire width 1 \oper_r__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 32 \oper_r__insn - process $group_42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 10 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__input_cr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__input_cr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_cr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_cr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 129 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $70 + parameter \WIDTH 129 + connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + connect \S \issue_i + connect \Y $69 + end + process $group_25 assign \oper_r__insn_type 7'0000000 assign \oper_r__fn_unit 10'0000000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -87118,45 +87052,139 @@ module \shiftrot0 assign \oper_r__is_32bit 1'0 assign \oper_r__is_signed 1'0 assign \oper_r__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69 + sync init + end + process $group_42 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm + assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok + assign \oper_l__rc__rc$next \oper_l__rc__rc + assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok + assign \oper_l__oe__oe$next \oper_l__oe__oe + assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok + assign \oper_l__write_cr__data$next \oper_l__write_cr__data + assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok + assign \oper_l__input_carry$next \oper_l__input_carry + assign \oper_l__output_carry$next \oper_l__output_carry + assign \oper_l__input_cr$next \oper_l__input_cr + assign \oper_l__output_cr$next \oper_l__output_cr + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__is_signed$next \oper_l__is_signed + assign \oper_l__insn$next \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_l__imm_data__imm_ok$next 1'0 + assign \oper_l__rc__rc$next 1'0 + assign \oper_l__rc__rc_ok$next 1'0 + assign \oper_l__oe__oe$next 1'0 + assign \oper_l__oe__oe_ok$next 1'0 + assign \oper_l__write_cr__data$next 3'000 + assign \oper_l__write_cr__ok$next 1'0 + assign \oper_l__insn$next 32'00000000000000000000000000000000 end sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 10'0000000000 + update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_l__imm_data__imm_ok 1'0 + update \oper_l__rc__rc 1'0 + update \oper_l__rc__rc_ok 1'0 + update \oper_l__oe__oe 1'0 + update \oper_l__oe__oe_ok 1'0 + update \oper_l__write_cr__data 3'000 + update \oper_l__write_cr__ok 1'0 + update \oper_l__input_carry 2'00 + update \oper_l__output_carry 1'0 + update \oper_l__input_cr 1'0 + update \oper_l__output_cr 1'0 + update \oper_l__is_32bit 1'0 + update \oper_l__is_signed 1'0 + update \oper_l__insn 32'00000000000000000000000000000000 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__imm_data__imm \oper_l__imm_data__imm$next + update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next + update \oper_l__rc__rc \oper_l__rc__rc$next + update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next + update \oper_l__oe__oe \oper_l__oe__oe$next + update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next + update \oper_l__write_cr__data \oper_l__write_cr__data$next + update \oper_l__write_cr__ok \oper_l__write_cr__ok$next + update \oper_l__input_carry \oper_l__input_carry$next + update \oper_l__output_carry \oper_l__output_carry$next + update \oper_l__input_cr \oper_l__input_cr$next + update \oper_l__output_cr \oper_l__output_cr$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__is_signed \oper_l__is_signed$next + update \oper_l__insn \oper_l__insn$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \data_r0_l__o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $74 + parameter \WIDTH 65 + connect \A { \data_r0_l__o_ok \data_r0_l__o } + connect \B { \o_ok \o } + connect \S $72 + connect \Y $71 + end + process $group_59 + assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__o_ok 1'0 + assign { \data_r0__o_ok \data_r0__o } $71 + sync init + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $69 + wire width 1 $75 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $70 + cell $reduce_bool $76 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $69 + connect \Y $75 end - process $group_59 + process $group_61 assign \data_r0_l__o$next \data_r0_l__o assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -87170,62 +87198,62 @@ module \shiftrot0 update \data_r0_l__o \data_r0_l__o$next update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 5 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $79 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $71 + connect \Y $78 end - process $group_61 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r0__o_ok \data_r0__o } { \o_ok \o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 5 + connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } + connect \B { \cr_a_ok \cr_a } + connect \S $78 + connect \Y $77 + end + process $group_63 + assign \data_r1__cr_a 4'0000 + assign \data_r1__cr_a_ok 1'0 + assign { \data_r1__cr_a_ok \data_r1__cr_a } $77 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r1_l__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $73 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $74 + cell $reduce_bool $82 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $73 + connect \Y $81 end - process $group_63 + process $group_65 assign \data_r1_l__cr_a$next \data_r1_l__cr_a assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -87239,62 +87267,62 @@ module \shiftrot0 update \data_r1_l__cr_a \data_r1_l__cr_a$next update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 3 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $85 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $75 + connect \Y $84 end - process $group_65 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r1__cr_a_ok \data_r1__cr_a } { \cr_a_ok \cr_a } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r1__cr_a_ok \data_r1__cr_a } { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 3 + connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } + connect \B { \xer_ca_ok \xer_ca } + connect \S $84 + connect \Y $83 + end + process $group_67 + assign \data_r2__xer_ca 2'00 + assign \data_r2__xer_ca_ok 1'0 + assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r2_l__xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 2 \data_r2_l__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \data_r2_l__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $77 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $78 + cell $reduce_bool $88 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_pulsem - connect \Y $77 + connect \Y $87 end - process $group_67 + process $group_69 assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -87308,243 +87336,215 @@ module \shiftrot0 update \data_r2_l__xer_ca \data_r2_l__xer_ca$next update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $79 - end - process $group_69 - assign \data_r2__xer_ca 2'00 - assign \data_r2__xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \xer_ca_ok \xer_ca } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } - end - sync init - end process $group_71 assign \wrmask 3'000 assign \wrmask { \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok } sync init end process $group_72 - assign \alu_op__insn_type 7'0000000 - assign \alu_op__fn_unit 10'0000000000 - assign \alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok 1'0 - assign \alu_op__rc__rc 1'0 - assign \alu_op__rc__rc_ok 1'0 - assign \alu_op__oe__oe 1'0 - assign \alu_op__oe__oe_ok 1'0 - assign \alu_op__write_cr__data 3'000 - assign \alu_op__write_cr__ok 1'0 - assign \alu_op__input_carry 2'00 - assign \alu_op__output_carry 1'0 - assign \alu_op__input_cr 1'0 - assign \alu_op__output_cr 1'0 - assign \alu_op__is_32bit 1'0 - assign \alu_op__is_signed 1'0 - assign \alu_op__insn 32'00000000000000000000000000000000 - assign { \alu_op__insn \alu_op__is_signed \alu_op__is_32bit \alu_op__output_cr \alu_op__input_cr \alu_op__output_carry \alu_op__input_carry { \alu_op__write_cr__ok \alu_op__write_cr__data } { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + assign \alu_shift_rot0_op__insn_type 7'0000000 + assign \alu_shift_rot0_op__fn_unit 10'0000000000 + assign \alu_shift_rot0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_op__imm_data__imm_ok 1'0 + assign \alu_shift_rot0_op__rc__rc 1'0 + assign \alu_shift_rot0_op__rc__rc_ok 1'0 + assign \alu_shift_rot0_op__oe__oe 1'0 + assign \alu_shift_rot0_op__oe__oe_ok 1'0 + assign \alu_shift_rot0_op__write_cr__data 3'000 + assign \alu_shift_rot0_op__write_cr__ok 1'0 + assign \alu_shift_rot0_op__input_carry 2'00 + assign \alu_shift_rot0_op__output_carry 1'0 + assign \alu_shift_rot0_op__input_cr 1'0 + assign \alu_shift_rot0_op__output_cr 1'0 + assign \alu_shift_rot0_op__is_32bit 1'0 + assign \alu_shift_rot0_op__is_signed 1'0 + assign \alu_shift_rot0_op__insn 32'00000000000000000000000000000000 + assign { \alu_shift_rot0_op__insn \alu_shift_rot0_op__is_signed \alu_shift_rot0_op__is_32bit \alu_shift_rot0_op__output_cr \alu_shift_rot0_op__input_cr \alu_shift_rot0_op__output_carry \alu_shift_rot0_op__input_carry { \alu_shift_rot0_op__write_cr__ok \alu_shift_rot0_op__write_cr__data } { \alu_shift_rot0_op__oe__oe_ok \alu_shift_rot0_op__oe__oe } { \alu_shift_rot0_op__rc__rc_ok \alu_shift_rot0_op__rc__rc } { \alu_shift_rot0_op__imm_data__imm_ok \alu_shift_rot0_op__imm_data__imm } \alu_shift_rot0_op__fn_unit \alu_shift_rot0_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 1 \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - cell $mux $82 + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $90 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \oper_r__imm_data__imm_ok - connect \Y $81 + connect \Y $89 end process $group_89 assign \src_sel 1'0 - assign \src_sel $81 + assign \src_sel $89 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $92 parameter \WIDTH 64 connect \A \src2_i connect \B \oper_r__imm_data__imm connect \S \oper_r__imm_data__imm_ok - connect \Y $83 + connect \Y $91 end process $group_90 assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $83 + assign \src_or_imm $91 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $94 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $93 + end process $group_91 + assign \alu_shift_rot0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_ra $93 + sync init + end + process $group_92 assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r0$next \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r0 \src_r0$next end - process $group_92 - assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_ra \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_ra \src_r0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $96 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $95 + end process $group_93 + assign \alu_shift_rot0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_rb $95 + sync init + end + process $group_94 assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r1$next \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r1 \src_r1$next end - process $group_94 - assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_rb \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_rb \src_r1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $98 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $97 + end process $group_95 + assign \alu_shift_rot0_rc 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_rc $97 + sync init + end + process $group_96 assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r2$next \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r2 \src_r2$next end - process $group_96 - assign \alu_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_rc \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_rc \src_r2 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 2 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 2 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $100 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $99 + end process $group_97 + assign \alu_shift_rot0_xer_ca 2'00 + assign \alu_shift_rot0_xer_ca $99 + sync init + end + process $group_98 assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r3$next \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r3 2'00 sync posedge \clk update \src_r3 \src_r3$next end - process $group_98 - assign \alu_xer_ca 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \alu_xer_ca \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \alu_xer_ca \src_r3 - end - sync init - end process $group_99 - assign \alu_p_valid_i 1'0 - assign \alu_p_valid_i \alui_l_q_alui + assign \alu_shift_rot0_p_valid_i 1'0 + assign \alu_shift_rot0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" - cell $and $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + cell $and $102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_p_ready_o + connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $85 + connect \Y $101 end process $group_100 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $85 + assign \alui_l_r_alui$next $101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -87561,26 +87561,26 @@ module \shiftrot0 sync init end process $group_102 - assign \alu_n_ready_i 1'0 - assign \alu_n_ready_i \alu_l_q_alu + assign \alu_shift_rot0_n_ready_i 1'0 + assign \alu_shift_rot0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + cell $and $104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_n_valid_o + connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $87 + connect \Y $103 end process $group_103 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $87 + assign \alu_l_r_alu$next $103 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -87601,10 +87601,10 @@ module \shiftrot0 assign \busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $106 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -87612,63 +87612,63 @@ module \shiftrot0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \busy_o \busy_o \busy_o \busy_o } - connect \Y $89 + connect \Y $105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" - cell $not $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \oper_r__imm_data__imm_ok - connect \Y $91 + connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $110 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $89 - connect \B { 1'1 1'1 $91 1'1 } - connect \Y $93 + connect \A $105 + connect \B { 1'1 1'1 $107 1'1 } + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $not $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $not $112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \rdmaskn - connect \Y $95 + connect \Y $111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - wire width 4 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" - cell $and $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 4 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $114 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $93 - connect \B $95 - connect \Y $97 + connect \A $109 + connect \B $111 + connect \Y $113 end process $group_106 assign \rd__rel 4'0000 - assign \rd__rel $97 + assign \rd__rel $113 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87676,12 +87676,12 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $99 + connect \Y $115 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87689,12 +87689,12 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $101 + connect \Y $117 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" - cell $and $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87702,44 +87702,44 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $103 + connect \Y $119 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $122 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req - connect \B { $99 $101 $103 } - connect \Y $105 + connect \B { $115 $117 $119 } + connect \Y $121 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 3 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $105 + connect \A $121 connect \B \wrmask - connect \Y $107 + connect \Y $123 end process $group_107 assign \wr__rel 3'000 - assign \wr__rel $107 + assign \wr__rel $123 sync init end process $group_108 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] end @@ -87749,9 +87749,9 @@ module \shiftrot0 wire width 4 \dest2_o process $group_109 assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] end @@ -87761,9 +87761,9 @@ module \shiftrot0 wire width 2 \dest3_o process $group_110 assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] end @@ -87772,24 +87772,24 @@ module \shiftrot0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" -module \opc_l$77 +module \opc_l$72 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_opc + wire width 1 input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87797,9 +87797,9 @@ module \opc_l$77 connect \A \r_opc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87810,9 +87810,9 @@ module \opc_l$77 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87836,9 +87836,9 @@ module \opc_l$77 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87846,9 +87846,9 @@ module \opc_l$77 connect \A \r_opc connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87859,9 +87859,9 @@ module \opc_l$77 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87877,11 +87877,11 @@ module \opc_l$77 assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87894,11 +87894,11 @@ module \opc_l$77 assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -87917,24 +87917,24 @@ module \opc_l$77 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" -module \src_l$78 +module \src_l$73 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \r_src + wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -87942,9 +87942,9 @@ module \src_l$78 connect \A \r_src connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -87955,9 +87955,9 @@ module \src_l$78 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -87981,9 +87981,9 @@ module \src_l$78 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -87991,9 +87991,9 @@ module \src_l$78 connect \A \r_src connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -88004,9 +88004,9 @@ module \src_l$78 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -88022,11 +88022,11 @@ module \src_l$78 assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -88039,11 +88039,11 @@ module \src_l$78 assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -88062,24 +88062,24 @@ module \src_l$78 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" -module \alu_l$79 +module \alu_l$74 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_alu + wire width 1 input 2 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88087,9 +88087,9 @@ module \alu_l$79 connect \A \r_alu connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88100,9 +88100,9 @@ module \alu_l$79 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88126,9 +88126,9 @@ module \alu_l$79 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88136,9 +88136,9 @@ module \alu_l$79 connect \A \r_alu connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88149,9 +88149,9 @@ module \alu_l$79 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88167,11 +88167,11 @@ module \alu_l$79 assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88184,11 +88184,11 @@ module \alu_l$79 assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88212,19 +88212,19 @@ module \adr_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_adr + wire width 1 input 2 \s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88232,9 +88232,9 @@ module \adr_l connect \A \r_adr connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88245,9 +88245,9 @@ module \adr_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88271,9 +88271,9 @@ module \adr_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88281,9 +88281,9 @@ module \adr_l connect \A \r_adr connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88294,9 +88294,9 @@ module \adr_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88312,11 +88312,11 @@ module \adr_l assign \q_adr $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88329,11 +88329,11 @@ module \adr_l assign \qn_adr $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88357,21 +88357,21 @@ module \lod_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 output 4 \qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 5 \q_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88379,9 +88379,9 @@ module \lod_l connect \A \r_lod connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88392,9 +88392,9 @@ module \lod_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88418,9 +88418,9 @@ module \lod_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88428,9 +88428,9 @@ module \lod_l connect \A \r_lod connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88441,9 +88441,9 @@ module \lod_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88459,9 +88459,9 @@ module \lod_l assign \q_lod $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88474,11 +88474,11 @@ module \lod_l assign \qn_lod $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88502,19 +88502,19 @@ module \sto_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_sto + wire width 1 input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88522,9 +88522,9 @@ module \sto_l connect \A \r_sto connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88535,9 +88535,9 @@ module \sto_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88561,9 +88561,9 @@ module \sto_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88571,9 +88571,9 @@ module \sto_l connect \A \r_sto connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88584,9 +88584,9 @@ module \sto_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88602,11 +88602,11 @@ module \sto_l assign \q_sto $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88619,11 +88619,11 @@ module \sto_l assign \qn_sto $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88647,19 +88647,19 @@ module \wri_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_wri + wire width 1 input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88667,9 +88667,9 @@ module \wri_l connect \A \r_wri connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88680,9 +88680,9 @@ module \wri_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88706,9 +88706,9 @@ module \wri_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88716,9 +88716,9 @@ module \wri_l connect \A \r_wri connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88729,9 +88729,9 @@ module \wri_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88747,11 +88747,11 @@ module \wri_l assign \q_wri $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88764,11 +88764,11 @@ module \wri_l assign \qn_wri $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88792,19 +88792,19 @@ module \upd_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_upd + wire width 1 input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88812,9 +88812,9 @@ module \upd_l connect \A \r_upd connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88825,9 +88825,9 @@ module \upd_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88851,9 +88851,9 @@ module \upd_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88861,9 +88861,9 @@ module \upd_l connect \A \r_upd connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88874,9 +88874,9 @@ module \upd_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88892,11 +88892,11 @@ module \upd_l assign \q_upd $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88909,11 +88909,11 @@ module \upd_l assign \qn_upd $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88932,24 +88932,24 @@ module \upd_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" -module \rst_l$80 +module \rst_l$75 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_rst + wire width 1 input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88957,9 +88957,9 @@ module \rst_l$80 connect \A \r_rst connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88970,9 +88970,9 @@ module \rst_l$80 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -88996,9 +88996,9 @@ module \rst_l$80 sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89006,9 +89006,9 @@ module \rst_l$80 connect \A \r_rst connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89019,9 +89019,9 @@ module \rst_l$80 connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89037,11 +89037,11 @@ module \rst_l$80 assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89054,11 +89054,11 @@ module \rst_l$80 assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -89236,60 +89236,60 @@ module \ldst0 wire width 64 output 41 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 42 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$77 \opc_l + cell \opc_l$72 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc connect \r_opc \opc_l_r_opc connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src - cell \src_l$78 \src_l + cell \src_l$73 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src connect \r_src \src_l_r_src connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_r_alu + wire width 1 \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - cell \alu_l$79 \alu_l + cell \alu_l$74 \alu_l connect \rst \rst connect \clk \clk connect \s_alu \alu_l_s_alu connect \r_alu \alu_l_r_alu connect \q_alu \alu_l_q_alu end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \adr_l_s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \adr_l_s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \adr_l_r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \adr_l_r_adr$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \adr_l_r_adr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \adr_l_q_adr cell \adr_l \adr_l connect \rst \rst @@ -89298,13 +89298,13 @@ module \ldst0 connect \r_adr \adr_l_r_adr connect \q_adr \adr_l_q_adr end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \lod_l_s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \lod_l_s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \lod_l_r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \lod_l_qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \lod_l_q_lod cell \lod_l \lod_l connect \rst \rst @@ -89314,11 +89314,11 @@ module \ldst0 connect \qn_lod \lod_l_qn_lod connect \q_lod \lod_l_q_lod end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \sto_l_s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \sto_l_r_sto + wire width 1 \sto_l_s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \sto_l_r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \sto_l_q_sto cell \sto_l \sto_l connect \rst \rst @@ -89327,13 +89327,13 @@ module \ldst0 connect \r_sto \sto_l_r_sto connect \q_sto \sto_l_q_sto end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \wri_l_s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \wri_l_r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \wri_l_r_wri$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \wri_l_r_wri$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \wri_l_q_wri cell \wri_l \wri_l connect \rst \rst @@ -89342,15 +89342,15 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \q_wri \wri_l_q_wri end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \upd_l_s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \upd_l_s_upd$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \upd_l_s_upd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \upd_l_r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \upd_l_r_upd$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \upd_l_r_upd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \upd_l_q_upd cell \upd_l \upd_l connect \rst \rst @@ -89359,13 +89359,13 @@ module \ldst0 connect \r_upd \upd_l_r_upd connect \q_upd \upd_l_q_upd end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_r_rst + wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rst_l_q_rst - cell \rst_l$80 \rst_l + cell \rst_l$75 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -89760,117 +89760,29 @@ module \ldst0 wire width 1 $28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $28 - end - process $group_23 - assign \sto_l_r_sto 1'1 - assign \sto_l_r_sto $28 - sync init - end - process $group_24 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \addr_ok - sync init - end - process $group_25 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \issue_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__byte_reverse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__byte_reverse$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__sign_extend - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__sign_extend$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__update - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" - wire width 1 \oper_l__update$next - process $group_26 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len - assign \oper_l__byte_reverse$next \oper_l__byte_reverse - assign \oper_l__sign_extend$next \oper_l__sign_extend - assign \oper_l__update$next \oper_l__update - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { \oper_l__update$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - end + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $28 + end + process $group_23 + assign \sto_l_r_sto 1'1 + assign \sto_l_r_sto $28 + sync init + end + process $group_24 + assign \rst_l_s_rst 1'0 + assign \rst_l_s_rst \addr_ok + sync init + end + process $group_25 + assign \rst_l_r_rst 1'1 + assign \rst_l_r_rst \issue_i sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 - update \oper_l__byte_reverse 1'0 - update \oper_l__sign_extend 1'0 - update \oper_l__update 1'0 - sync posedge \clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next - update \oper_l__byte_reverse \oper_l__byte_reverse$next - update \oper_l__sign_extend \oper_l__sign_extend$next - update \oper_l__update \oper_l__update$next end attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -89964,7 +89876,57 @@ module \ldst0 wire width 1 \oper_r__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" wire width 1 \oper_r__update - process $group_36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__byte_reverse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__sign_extend + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__sign_extend$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__update + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__update$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 82 $30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $31 + parameter \WIDTH 82 + connect \A { \oper_l__update \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type } + connect \B { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type } + connect \S \issue_i + connect \Y $30 + end + process $group_26 assign \oper_r__insn_type 7'0000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \oper_r__imm_data__imm_ok 1'0 @@ -89975,66 +89937,119 @@ module \ldst0 assign \oper_r__byte_reverse 1'0 assign \oper_r__sign_extend 1'0 assign \oper_r__update 1'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { \oper_r__update \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $30 + sync init + end + process $group_36 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm + assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok + assign \oper_l__zero_a$next \oper_l__zero_a + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__is_signed$next \oper_l__is_signed + assign \oper_l__data_len$next \oper_l__data_len + assign \oper_l__byte_reverse$next \oper_l__byte_reverse + assign \oper_l__sign_extend$next \oper_l__sign_extend + assign \oper_l__update$next \oper_l__update + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_r__update \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { \oper_r__update \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } { \oper_l__update \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type } + assign { \oper_l__update$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_l__imm_data__imm_ok$next 1'0 end sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_l__imm_data__imm_ok 1'0 + update \oper_l__zero_a 1'0 + update \oper_l__is_32bit 1'0 + update \oper_l__is_signed 1'0 + update \oper_l__data_len 4'0000 + update \oper_l__byte_reverse 1'0 + update \oper_l__sign_extend 1'0 + update \oper_l__update 1'0 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__imm_data__imm \oper_l__imm_data__imm$next + update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next + update \oper_l__zero_a \oper_l__zero_a$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__is_signed \oper_l__is_signed$next + update \oper_l__data_len \oper_l__data_len$next + update \oper_l__byte_reverse \oper_l__byte_reverse$next + update \oper_l__sign_extend \oper_l__sign_extend$next + update \oper_l__update \oper_l__update$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" - wire width 64 \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" - wire width 64 \ldo_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:361" + wire width 64 \ldd_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278" wire width 64 \ldd_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $33 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $32 + end process $group_46 + assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ldd_r $32 + sync init + end + process $group_47 assign \ldo_r$next \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \ld_ok } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \ldo_r$next \ldd_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \ldo_r 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \ldo_r \ldo_r$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:361" - wire width 64 \ldd_r - process $group_47 - assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \ld_ok } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \ldd_r \ldd_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \ldd_r \ldo_r - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0_l$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $35 + parameter \WIDTH 64 + connect \A \src_r0_l + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $34 + end process $group_48 + assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_r0 $34 + sync init + end + process $group_49 assign \src_r0_l$next \src_r0_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r0_l$next \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r0_l 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -90042,33 +90057,33 @@ module \ldst0 update \src_r0_l \src_r0_l$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - wire width 64 \src_r0 - process $group_49 - assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \src_r0 \src1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \src_r0 \src_r0_l - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1_l$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $37 + parameter \WIDTH 64 + connect \A \src_r1_l + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $36 + end process $group_50 + assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_r1 $36 + sync init + end + process $group_51 assign \src_r1_l$next \src_r1_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r1_l$next \src2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r1_l 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -90076,132 +90091,117 @@ module \ldst0 update \src_r1_l \src_r1_l$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - wire width 64 \src_r1 - process $group_51 - assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \src_r1 \src2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \src_r1 \src_r1_l - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r2_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r2_l$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $39 + parameter \WIDTH 64 + connect \A \src_r2_l + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $38 + end process $group_52 + assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_r2 $38 + sync init + end + process $group_53 assign \src_r2_l$next \src_r2_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \src_r2_l$next \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \src_r2_l 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r2_l \src_r2_l$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - wire width 64 \src_r2 - process $group_53 - assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \src_r2 \src3_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \src_r2 \src_r2_l - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" - wire width 64 \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" - wire width 64 \ea_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" + wire width 64 \addr_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" wire width 64 \alu_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" wire width 64 \alu_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $41 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $40 + end process $group_54 + assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \addr_r $40 + sync init + end + process $group_55 assign \ea_r$next \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \alu_l_q_alu } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 assign \ea_r$next \alu_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case end sync init update \ea_r 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \ea_r \ea_r$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" - wire width 64 \addr_r - process $group_55 - assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \alu_l_q_alu } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign \addr_r \alu_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign \addr_r \ea_r - end - sync init - end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" wire width 64 \src1_or_z attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" - wire width 64 $30 + wire width 64 $42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" - cell $mux $31 + cell $mux $43 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $30 + connect \Y $42 end process $group_56 assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_or_z $30 + assign \src1_or_z $42 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:383" wire width 64 \src2_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" - wire width 64 $32 + wire width 64 $44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" - cell $mux $33 + cell $mux $45 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__imm connect \S \oper_r__imm_data__imm_ok - connect \Y $32 + connect \Y $44 end process $group_57 assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_or_imm $32 + assign \src2_or_imm $44 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387" - wire width 65 $34 + wire width 65 $46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387" - wire width 65 $35 + wire width 65 $47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387" - cell $add $36 + cell $add $48 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -90209,12 +90209,12 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $35 + connect \Y $47 end - connect $34 $35 + connect $46 $47 process $group_58 assign \alu_o$next \alu_o - assign \alu_o$next $34 [63:0] + assign \alu_o$next $46 [63:0] sync init update \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk @@ -90229,9 +90229,9 @@ module \ldst0 update \alu_ok \alu_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 1 $37 + wire width 1 $49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - cell $eq $38 + cell $eq $50 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -90239,19 +90239,19 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $37 + connect \Y $49 end process $group_60 assign \op_is_st 1'0 - assign \op_is_st $37 + assign \op_is_st $49 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:263" wire width 1 \op_is_ld attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - wire width 1 $39 + wire width 1 $51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - cell $eq $40 + cell $eq $52 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -90259,17 +90259,17 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $39 + connect \Y $51 end process $group_61 assign \op_is_ld 1'0 - assign \op_is_ld $39 + assign \op_is_ld $51 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - wire width 1 $41 + wire width 1 $53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - cell $and $42 + cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90277,17 +90277,17 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \ad__go - connect \Y $41 + connect \Y $53 end process $group_62 assign \load_mem_o 1'0 - assign \load_mem_o $41 + assign \load_mem_o $53 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" - wire width 1 $43 + wire width 1 $55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" - cell $and $44 + cell $and $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90295,11 +90295,11 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \st__go - connect \Y $43 + connect \Y $55 end process $group_63 assign \stwd_mem_o 1'0 - assign \stwd_mem_o $43 + assign \stwd_mem_o $55 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:108" @@ -90322,9 +90322,9 @@ module \ldst0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 3 $45 + wire width 3 $57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $and $46 + cell $and $58 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -90332,58 +90332,58 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \busy_o \busy_o \busy_o } - connect \Y $45 + connect \Y $57 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 2 $47 + wire width 2 $59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $not $48 + cell $not $60 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a } - connect \Y $47 + connect \Y $59 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 3 $49 + wire width 3 $61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $and $50 + cell $and $62 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 - connect \A $45 - connect \B $47 - connect \Y $49 + connect \A $57 + connect \B $59 + connect \Y $61 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 3 $51 + wire width 3 $63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $not $52 + cell $not $64 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \rdmaskn - connect \Y $51 + connect \Y $63 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 3 $53 + wire width 3 $65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $and $54 + cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $49 - connect \B $51 - connect \Y $53 + connect \A $61 + connect \B $63 + connect \Y $65 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419" - wire width 1 $55 + wire width 1 $67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419" - cell $and $56 + cell $and $68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90391,31 +90391,31 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \busy_o - connect \Y $55 + connect \Y $67 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419" - wire width 1 $57 + wire width 1 $69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419" - cell $and $58 + cell $and $70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $55 + connect \A $67 connect \B \op_is_st - connect \Y $57 + connect \Y $69 end process $group_67 assign \rd__rel 3'000 - assign \rd__rel $53 - assign \rd__rel [2] $57 + assign \rd__rel $65 + assign \rd__rel [2] $69 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - wire width 1 $59 + wire width 1 $71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - cell $or $60 + cell $or $72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90423,19 +90423,19 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd__go [0] connect \B \rd__go [1] - connect \Y $59 + connect \Y $71 end process $group_68 assign \rda_any 1'0 - assign \rda_any $59 + assign \rda_any $71 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 1 $61 + wire width 1 $73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 1 $62 + wire width 1 $74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $or $63 + cell $or $75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90443,68 +90443,68 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd__rel [0] connect \B \rd__rel [1] - connect \Y $62 + connect \Y $74 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $not $64 + cell $not $76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $62 - connect \Y $61 + connect \A $74 + connect \Y $73 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 1 $65 + wire width 1 $77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $and $66 + cell $and $78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_o - connect \B $61 - connect \Y $65 + connect \B $73 + connect \Y $77 end process $group_69 assign \alu_valid 1'0 - assign \alu_valid $65 + assign \alu_valid $77 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" wire width 1 \rd_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - wire width 1 $67 + wire width 1 $79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - cell $not $68 + cell $not $80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rd__rel [2] - connect \Y $67 + connect \Y $79 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - wire width 1 $69 + wire width 1 $81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - cell $and $70 + cell $and $82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \B $67 - connect \Y $69 + connect \B $79 + connect \Y $81 end process $group_70 assign \rd_done 1'0 - assign \rd_done $69 + assign \rd_done $81 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - wire width 1 $71 + wire width 1 $83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - cell $and $72 + cell $and $84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90512,30 +90512,30 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $71 + connect \Y $83 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - wire width 1 $73 + wire width 1 $85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - cell $and $74 + cell $and $86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $71 + connect \A $83 connect \B \busy_o - connect \Y $73 + connect \Y $85 end process $group_71 assign \ad__rel 1'0 - assign \ad__rel $73 + assign \ad__rel $85 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 1 $75 + wire width 1 $87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $76 + cell $and $88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90543,56 +90543,56 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \busy_o - connect \Y $75 + connect \Y $87 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 1 $77 + wire width 1 $89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $78 + cell $and $90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $75 + connect \A $87 connect \B \rd_done - connect \Y $77 + connect \Y $89 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 1 $79 + wire width 1 $91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $80 + cell $and $92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $77 + connect \A $89 connect \B \op_is_st - connect \Y $79 + connect \Y $91 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429" - wire width 1 $81 + wire width 1 $93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429" - cell $and $82 + cell $and $94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $79 + connect \A $91 connect \B \shadown_i - connect \Y $81 + connect \Y $93 end process $group_72 assign \st__rel 1'0 - assign \st__rel $81 + assign \st__rel $93 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $83 + wire width 1 $95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $84 + cell $and $96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90600,64 +90600,64 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $83 + connect \Y $95 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $85 + wire width 1 $97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $86 + cell $and $98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $83 + connect \A $95 connect \B \busy_o - connect \Y $85 + connect \Y $97 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $87 + wire width 1 $99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $88 + cell $and $100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $85 + connect \A $97 connect \B \lod_l_qn_lod - connect \Y $87 + connect \Y $99 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $89 + wire width 1 $101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $90 + cell $and $102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $87 + connect \A $99 connect \B \op_is_ld - connect \Y $89 + connect \Y $101 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $91 + wire width 1 $103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $92 + cell $and $104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $89 + connect \A $101 connect \B \shadown_i - connect \Y $91 + connect \Y $103 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - wire width 1 $93 + wire width 1 $105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - cell $and $94 + cell $and $106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90665,46 +90665,46 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \busy_o - connect \Y $93 + connect \Y $105 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - wire width 1 $95 + wire width 1 $107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - cell $and $96 + cell $and $108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $93 + connect \A $105 connect \B \oper_r__update - connect \Y $95 + connect \Y $107 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - wire width 1 $97 + wire width 1 $109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $98 + cell $and $110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $95 + connect \A $107 connect \B \shadown_i - connect \Y $97 + connect \Y $109 end process $group_73 assign \wr__rel 2'00 - assign \wr__rel [0] $91 - assign \wr__rel [1] $97 + assign \wr__rel [0] $103 + assign \wr__rel [1] $109 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" wire width 1 \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - wire width 1 $99 + wire width 1 $111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $or $100 + cell $or $112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90712,43 +90712,43 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \st__go connect \B \p_st_go - connect \Y $99 + connect \Y $111 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - wire width 1 $101 + wire width 1 $113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $or $102 + cell $or $114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $99 + connect \A $111 connect \B \wr__go [0] - connect \Y $101 + connect \Y $113 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - wire width 1 $103 + wire width 1 $115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $or $104 + cell $or $116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $101 + connect \A $113 connect \B \wr__go [1] - connect \Y $103 + connect \Y $115 end process $group_74 assign \wr_any 1'0 - assign \wr_any $103 + assign \wr_any $115 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $105 + wire width 1 $117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $106 + cell $and $118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90756,27 +90756,27 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \busy_o - connect \Y $105 + connect \Y $117 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $107 + wire width 1 $119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $108 + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $105 + connect \A $117 connect \B \shadown_i - connect \Y $107 + connect \Y $119 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $109 + wire width 1 $121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $110 + wire width 1 $122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $or $111 + cell $or $123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90784,46 +90784,46 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \st__rel connect \B \wr__rel [0] - connect \Y $110 + connect \Y $122 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $112 + wire width 1 $124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $or $113 + cell $or $125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $110 + connect \A $122 connect \B \wr__rel [1] - connect \Y $112 + connect \Y $124 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $not $114 + cell $not $126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $112 - connect \Y $109 + connect \A $124 + connect \Y $121 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $115 + wire width 1 $127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $116 + cell $and $128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $107 - connect \B $109 - connect \Y $115 + connect \A $119 + connect \B $121 + connect \Y $127 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - wire width 1 $117 + wire width 1 $129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $or $118 + cell $or $130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90831,24 +90831,24 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $117 + connect \Y $129 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - wire width 1 $119 + wire width 1 $131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $120 + cell $and $132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $115 - connect \B $117 - connect \Y $119 + connect \A $127 + connect \B $129 + connect \Y $131 end process $group_75 assign \wr_reset 1'0 - assign \wr_reset $119 + assign \wr_reset $131 sync init end process $group_76 @@ -90881,9 +90881,9 @@ module \ldst0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" - wire width 1 $121 + wire width 1 $133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" - cell $and $122 + cell $and $134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90891,12 +90891,12 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__update connect \B \wr__go [1] - connect \Y $121 + connect \Y $133 end process $group_80 assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" - switch { $121 } + switch { $133 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456" case 1'1 assign \dest2_o \addr_r @@ -90906,11 +90906,11 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" wire width 2 \wrmask attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 3 $123 + wire width 3 $135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 3 $124 + wire width 3 $136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $and $125 + cell $and $137 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -90918,18 +90918,18 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \busy_o \busy_o \busy_o } connect \B { \oper_r__update \op_is_ld } - connect \Y $124 + connect \Y $136 end - connect $123 $124 + connect $135 $136 process $group_81 assign \wrmask 2'00 - assign \wrmask $123 [1:0] + assign \wrmask $135 [1:0] sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:468" - wire width 1 $126 + wire width 1 $138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:468" - cell $and $127 + cell $and $139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90937,17 +90937,17 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \busy_o - connect \Y $126 + connect \Y $138 end process $group_82 assign \ldst_port0_is_ld_i 1'0 - assign \ldst_port0_is_ld_i $126 + assign \ldst_port0_is_ld_i $138 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" - wire width 1 $128 + wire width 1 $140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" - cell $and $129 + cell $and $141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90955,11 +90955,11 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \busy_o - connect \Y $128 + connect \Y $140 end process $group_83 assign \ldst_port0_is_st_i 1'0 - assign \ldst_port0_is_st_i $128 + assign \ldst_port0_is_st_i $140 sync init end process $group_84 @@ -90968,24 +90968,24 @@ module \ldst0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" - wire width 96 $130 + wire width 96 $142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" - cell $pos $131 + cell $pos $143 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $130 + connect \Y $142 end process $group_85 assign \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \ldst_port0_addr_i $130 + assign \ldst_port0_addr_i $142 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" - wire width 1 $132 + wire width 1 $144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" - cell $or $133 + cell $or $145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90993,24 +90993,24 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_q_lod connect \B \sto_l_q_sto - connect \Y $132 + connect \Y $144 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" - wire width 1 $134 + wire width 1 $146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473" - cell $and $135 + cell $and $147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_ok - connect \B $132 - connect \Y $134 + connect \B $144 + connect \Y $146 end process $group_86 assign \ldst_port0_addr_i_ok 1'0 - assign \ldst_port0_addr_i_ok $134 + assign \ldst_port0_addr_i_ok $146 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:106" @@ -92515,19 +92515,19 @@ module \st_active wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 3 \q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92535,9 +92535,9 @@ module \st_active connect \A \r_st_active connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92548,9 +92548,9 @@ module \st_active connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92574,9 +92574,9 @@ module \st_active sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92584,9 +92584,9 @@ module \st_active connect \A \r_st_active connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92597,9 +92597,9 @@ module \st_active connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92615,11 +92615,11 @@ module \st_active assign \q_st_active $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92632,11 +92632,11 @@ module \st_active assign \qn_st_active $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92660,19 +92660,19 @@ module \ld_active wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 3 \q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92680,9 +92680,9 @@ module \ld_active connect \A \r_ld_active connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92693,9 +92693,9 @@ module \ld_active connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92719,9 +92719,9 @@ module \ld_active sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92729,9 +92729,9 @@ module \ld_active connect \A \r_ld_active connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92742,9 +92742,9 @@ module \ld_active connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92760,11 +92760,11 @@ module \ld_active assign \q_ld_active $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92777,11 +92777,11 @@ module \ld_active assign \qn_ld_active $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92805,19 +92805,19 @@ module \reset_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_reset + wire width 1 input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92825,9 +92825,9 @@ module \reset_l connect \A \r_reset connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92838,9 +92838,9 @@ module \reset_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92869,11 +92869,11 @@ module \reset_l assign \q_reset \q_int sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92886,11 +92886,11 @@ module \reset_l assign \qn_reset $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92914,21 +92914,21 @@ module \adrok_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 3 \r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 output 4 \qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 5 \q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92936,9 +92936,9 @@ module \adrok_l connect \A \r_addr_acked connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92949,9 +92949,9 @@ module \adrok_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92975,9 +92975,9 @@ module \adrok_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92985,9 +92985,9 @@ module \adrok_l connect \A \r_addr_acked connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -92998,9 +92998,9 @@ module \adrok_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93016,9 +93016,9 @@ module \adrok_l assign \q_addr_acked $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93031,11 +93031,11 @@ module \adrok_l assign \qn_addr_acked $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93059,19 +93059,19 @@ module \busy_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_busy + wire width 1 input 2 \s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93079,9 +93079,9 @@ module \busy_l connect \A \r_busy connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93092,9 +93092,9 @@ module \busy_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93118,9 +93118,9 @@ module \busy_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93128,9 +93128,9 @@ module \busy_l connect \A \r_busy connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93141,9 +93141,9 @@ module \busy_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93159,11 +93159,11 @@ module \busy_l assign \q_busy $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93176,11 +93176,11 @@ module \busy_l assign \qn_busy $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93204,19 +93204,19 @@ module \cyc_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_cyc + wire width 1 input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93224,9 +93224,9 @@ module \cyc_l connect \A \r_cyc connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93237,9 +93237,9 @@ module \cyc_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93268,11 +93268,11 @@ module \cyc_l assign \q_cyc \q_int sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93285,11 +93285,11 @@ module \cyc_l assign \qn_cyc $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93394,19 +93394,19 @@ module \valid_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 3 \q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93414,9 +93414,9 @@ module \valid_l connect \A \r_valid connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93427,9 +93427,9 @@ module \valid_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93453,9 +93453,9 @@ module \valid_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93463,9 +93463,9 @@ module \valid_l connect \A \r_valid connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93476,9 +93476,9 @@ module \valid_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93494,11 +93494,11 @@ module \valid_l assign \q_valid $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93511,11 +93511,11 @@ module \valid_l assign \qn_valid $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -93581,11 +93581,11 @@ module \pimem wire width 1 output 21 \m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" wire width 1 output 22 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \st_active_s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \st_active_q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \st_active_r_st_active cell \st_active \st_active connect \rst \rst @@ -93594,11 +93594,11 @@ module \pimem connect \q_st_active \st_active_q_st_active connect \r_st_active \st_active_r_st_active end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \ld_active_s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \ld_active_q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \ld_active_r_ld_active cell \ld_active \ld_active connect \rst \rst @@ -93607,11 +93607,11 @@ module \pimem connect \q_ld_active \ld_active_q_ld_active connect \r_ld_active \ld_active_r_ld_active end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \reset_l_r_reset + wire width 1 \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \reset_l_q_reset cell \reset_l \reset_l connect \rst \rst @@ -93620,15 +93620,15 @@ module \pimem connect \r_reset \reset_l_r_reset connect \q_reset \reset_l_q_reset end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \adrok_l_s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \adrok_l_s_addr_acked$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \adrok_l_s_addr_acked$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \adrok_l_r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \adrok_l_qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \adrok_l_q_addr_acked cell \adrok_l \adrok_l connect \rst \rst @@ -93638,11 +93638,11 @@ module \pimem connect \qn_addr_acked \adrok_l_qn_addr_acked connect \q_addr_acked \adrok_l_q_addr_acked end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \busy_l_s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \busy_l_r_busy + wire width 1 \busy_l_s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \busy_l_r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \busy_l_q_busy cell \busy_l \busy_l connect \rst \rst @@ -93651,11 +93651,11 @@ module \pimem connect \r_busy \busy_l_r_busy connect \q_busy \busy_l_q_busy end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \cyc_l_s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \cyc_l_r_cyc + wire width 1 \cyc_l_s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \cyc_l_r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \cyc_l_q_cyc cell \cyc_l \cyc_l connect \rst \rst @@ -93678,11 +93678,11 @@ module \pimem connect \lexp_o \lenexp_lexp_o connect \rexp_o \lenexp_rexp_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \valid_l_s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \valid_l_q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \valid_l_r_valid cell \valid_l \valid_l connect \rst \rst @@ -94448,19 +94448,19 @@ module \idx_l wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 input 4 \r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94468,9 +94468,9 @@ module \idx_l connect \A \r_idx_l connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94481,9 +94481,9 @@ module \idx_l connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94507,9 +94507,9 @@ module \idx_l sync posedge \clk update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94517,9 +94517,9 @@ module \idx_l connect \A \r_idx_l connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94530,9 +94530,9 @@ module \idx_l connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94548,11 +94548,11 @@ module \idx_l assign \q_idx_l $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94565,11 +94565,11 @@ module \idx_l assign \qn_idx_l $13 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94588,24 +94588,24 @@ module \idx_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" -module \reset_l$82 +module \reset_l$77 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \r_reset + wire width 1 input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94613,9 +94613,9 @@ module \reset_l$82 connect \A \r_reset connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94626,9 +94626,9 @@ module \reset_l$82 connect \B $1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94657,11 +94657,11 @@ module \reset_l$82 assign \q_reset \q_int sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire width 1 \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94674,11 +94674,11 @@ module \reset_l$82 assign \qn_reset $7 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" wire width 1 \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -94735,7 +94735,7 @@ module \pick end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0" -module \l0$81 +module \l0$76 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -94792,11 +94792,11 @@ module \l0$81 wire width 1 input 26 \ldst_port0_go_die_i$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 1 output 27 \ldst_port0_busy_o$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \idx_l_q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \idx_l_s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \idx_l_s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \idx_l_r_idx_l cell \idx_l \idx_l connect \rst \rst @@ -94805,13 +94805,13 @@ module \l0$81 connect \s_idx_l \idx_l_s_idx_l connect \r_idx_l \idx_l_r_idx_l end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" - wire width 1 \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \reset_l_r_reset + wire width 1 \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \reset_l_q_reset - cell \reset_l$82 \reset_l + cell \reset_l$77 \reset_l connect \rst \rst connect \clk \clk connect \s_reset \reset_l_s_reset @@ -94847,57 +94847,60 @@ module \l0$81 assign \pick_i { $14 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" - wire width 1 \idx_l$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" - wire width 1 \idx_l$16$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \idx_l$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \idx_l$17$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $19 + parameter \WIDTH 1 + connect \A \idx_l$17 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $18 + end + connect $16 $18 process $group_1 - assign \idx_l$16$next \idx_l$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + assign { } 0'0 + assign { } {} + sync init + end + process $group_2 + assign \idx_l$17$next \idx_l$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \idx_l$16$next \pick_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case + assign \idx_l$17$next \pick_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \idx_l$16$next 1'0 + assign \idx_l$17$next 1'0 end sync init - update \idx_l$16 1'0 + update \idx_l$17 1'0 sync posedge \clk - update \idx_l$16 \idx_l$16$next - end - process $group_2 - assign { } 0'0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - case 1'1 - assign { } {} - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" - case - assign { } {} - end - sync init + update \idx_l$17 \idx_l$17$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237" - wire width 1 $17 + wire width 1 $20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237" - cell $not $18 + cell $not $21 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $17 + connect \Y $20 end process $group_3 assign \idx_l_s_idx_l 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237" - switch { $17 } + switch { $20 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237" case 1'1 assign \idx_l_s_idx_l 1'1 @@ -94905,14 +94908,14 @@ module \l0$81 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247" - wire width 1 $19 + wire width 1 $22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247" - cell $not $20 + cell $not $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $19 + connect \Y $22 end process $group_4 assign \reset_l_s_reset 1'0 @@ -94922,7 +94925,7 @@ module \l0$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245" case 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247" - switch { $19 } + switch { $22 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247" case 1'1 assign \reset_l_s_reset 1'1 @@ -94998,10 +95001,10 @@ module \l0$81 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" - wire width 96 $21 + wire width 96 $24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" - wire width 96 $22 - connect $22 \ldst_port0_addr_i + wire width 96 $25 + connect $25 \ldst_port0_addr_i process $group_10 assign \ldst_port0_addr_i$4 48'000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245" @@ -95011,7 +95014,7 @@ module \l0$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" switch { } case 0' - assign \ldst_port0_addr_i$4 $22 [47:0] + assign \ldst_port0_addr_i$4 $25 [47:0] end end sync init @@ -96132,7 +96135,7 @@ module \l0 connect \m_valid_i \m_valid_i connect \x_valid_i \x_valid_i end - cell \l0$81 \l0 + cell \l0$76 \l0 connect \rst \rst connect \clk \clk connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i @@ -109657,7 +109660,7 @@ module \int end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" -module \reg_0$83 +module \reg_0$78 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -110143,7 +110146,7 @@ module \reg_0$83 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" -module \reg_1$84 +module \reg_1$79 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -110629,7 +110632,7 @@ module \reg_1$84 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" -module \reg_2$85 +module \reg_2$80 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -111115,7 +111118,7 @@ module \reg_2$85 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" -module \reg_3$86 +module \reg_3$81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -111601,7 +111604,7 @@ module \reg_3$86 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" -module \reg_4$87 +module \reg_4$82 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -112087,7 +112090,7 @@ module \reg_4$87 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" -module \reg_5$88 +module \reg_5$83 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -112573,7 +112576,7 @@ module \reg_5$88 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" -module \reg_6$89 +module \reg_6$84 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -113059,7 +113062,7 @@ module \reg_6$89 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" -module \reg_7$90 +module \reg_7$85 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -113602,7 +113605,7 @@ module \cr wire width 4 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen - cell \reg_0$83 \reg_0 + cell \reg_0$78 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -113648,7 +113651,7 @@ module \cr wire width 4 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen - cell \reg_1$84 \reg_1 + cell \reg_1$79 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -113694,7 +113697,7 @@ module \cr wire width 4 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen - cell \reg_2$85 \reg_2 + cell \reg_2$80 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -113740,7 +113743,7 @@ module \cr wire width 4 \reg_3_w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_3_w3__wen - cell \reg_3$86 \reg_3 + cell \reg_3$81 \reg_3 connect \rst \rst connect \clk \clk connect \src13__ren \reg_3_src13__ren @@ -113786,7 +113789,7 @@ module \cr wire width 4 \reg_4_w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_4_w4__wen - cell \reg_4$87 \reg_4 + cell \reg_4$82 \reg_4 connect \rst \rst connect \clk \clk connect \src14__ren \reg_4_src14__ren @@ -113832,7 +113835,7 @@ module \cr wire width 4 \reg_5_w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_5_w5__wen - cell \reg_5$88 \reg_5 + cell \reg_5$83 \reg_5 connect \rst \rst connect \clk \clk connect \src15__ren \reg_5_src15__ren @@ -113878,7 +113881,7 @@ module \cr wire width 4 \reg_6_w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_6_w6__wen - cell \reg_6$89 \reg_6 + cell \reg_6$84 \reg_6 connect \rst \rst connect \clk \clk connect \src16__ren \reg_6_src16__ren @@ -113924,7 +113927,7 @@ module \cr wire width 4 \reg_7_w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_7_w7__wen - cell \reg_7$90 \reg_7 + cell \reg_7$85 \reg_7 connect \rst \rst connect \clk \clk connect \src17__ren \reg_7_src17__ren @@ -114420,7 +114423,7 @@ module \cr end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" -module \reg_0$91 +module \reg_0$86 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -114964,7 +114967,7 @@ module \reg_0$91 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" -module \reg_1$92 +module \reg_1$87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -115508,7 +115511,7 @@ module \reg_1$92 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" -module \reg_2$93 +module \reg_2$88 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -116109,7 +116112,7 @@ module \xer wire width 2 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen - cell \reg_0$91 \reg_0 + cell \reg_0$86 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -116161,7 +116164,7 @@ module \xer wire width 2 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen - cell \reg_1$92 \reg_1 + cell \reg_1$87 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -116213,7 +116216,7 @@ module \xer wire width 2 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen - cell \reg_2$93 \reg_2 + cell \reg_2$88 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -116458,7 +116461,7 @@ module \xer end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0" -module \reg_0$94 +module \reg_0$89 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -117192,7 +117195,7 @@ module \reg_0$94 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1" -module \reg_1$95 +module \reg_1$90 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -117926,7 +117929,7 @@ module \reg_1$95 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2" -module \reg_2$96 +module \reg_2$91 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -118660,7 +118663,7 @@ module \reg_2$96 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3" -module \reg_3$97 +module \reg_3$92 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -119394,7 +119397,7 @@ module \reg_3$97 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4" -module \reg_4$98 +module \reg_4$93 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -120128,7 +120131,7 @@ module \reg_4$98 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_5" -module \reg_5$99 +module \reg_5$94 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -120862,7 +120865,7 @@ module \reg_5$99 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_6" -module \reg_6$100 +module \reg_6$95 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -121596,7 +121599,7 @@ module \reg_6$100 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_7" -module \reg_7$101 +module \reg_7$96 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -122415,7 +122418,7 @@ module \fast wire width 1 \reg_0_d_wr10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_0_d_wr10__data_i - cell \reg_0$94 \reg_0 + cell \reg_0$89 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -122479,7 +122482,7 @@ module \fast wire width 1 \reg_1_d_wr11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_1_d_wr11__data_i - cell \reg_1$95 \reg_1 + cell \reg_1$90 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -122543,7 +122546,7 @@ module \fast wire width 1 \reg_2_d_wr12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_2_d_wr12__data_i - cell \reg_2$96 \reg_2 + cell \reg_2$91 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -122607,7 +122610,7 @@ module \fast wire width 1 \reg_3_d_wr13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_3_d_wr13__data_i - cell \reg_3$97 \reg_3 + cell \reg_3$92 \reg_3 connect \rst \rst connect \clk \clk connect \src13__ren \reg_3_src13__ren @@ -122671,7 +122674,7 @@ module \fast wire width 1 \reg_4_d_wr14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_4_d_wr14__data_i - cell \reg_4$98 \reg_4 + cell \reg_4$93 \reg_4 connect \rst \rst connect \clk \clk connect \src14__ren \reg_4_src14__ren @@ -122735,7 +122738,7 @@ module \fast wire width 1 \reg_5_d_wr15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_5_d_wr15__data_i - cell \reg_5$99 \reg_5 + cell \reg_5$94 \reg_5 connect \rst \rst connect \clk \clk connect \src15__ren \reg_5_src15__ren @@ -122799,7 +122802,7 @@ module \fast wire width 1 \reg_6_d_wr16__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_6_d_wr16__data_i - cell \reg_6$100 \reg_6 + cell \reg_6$95 \reg_6 connect \rst \rst connect \clk \clk connect \src16__ren \reg_6_src16__ren @@ -122863,7 +122866,7 @@ module \fast wire width 1 \reg_7_d_wr17__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_7_d_wr17__data_i - cell \reg_7$101 \reg_7 + cell \reg_7$96 \reg_7 connect \rst \rst connect \clk \clk connect \src17__ren \reg_7_src17__ren