From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 16:01:10 +0000 (-0700)
Subject: Format some names using inline code
X-Git-Tag: yosys-0.9~168
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6156f3118f327986d801fb48e50b94b7ea9e4b6;p=yosys.git

Format some names using inline code
---

diff --git a/README.md b/README.md
index 7b4477053..913777f2e 100644
--- a/README.md
+++ b/README.md
@@ -457,7 +457,7 @@ Non-standard or SystemVerilog features for formal verification
   supported in any clocked block.
 
 - The syntax ``@($global_clock)`` can be used to create FFs that have no
-  explicit clock input ($ff cells). The same can be achieved by using
+  explicit clock input (``$ff`` cells). The same can be achieved by using
   ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
   is marked with the ``(* gclk *)`` Verilog attribute.
 
@@ -470,7 +470,7 @@ from SystemVerilog:
 
 - The ``assert`` statement from SystemVerilog is supported in its most basic
   form. In module context: ``assert property (<expression>);`` and within an
-  always block: ``assert(<expression>);``. It is transformed to a $assert cell.
+  always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
 
 - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
   also supported. The same limitations as with the ``assert`` statement apply.