From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 13 Apr 2013 19:18:24 +0000 (+0200)
Subject: Fixed a bug in opt_const when optimizing 1-bit compares with constants
X-Git-Tag: yosys-0.2.0~650
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6198ea5a833008789ecbc9cc4da3ab61fcf4e82;p=yosys.git

Fixed a bug in opt_const when optimizing 1-bit compares with constants
---

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 0effd964b..7c82f0fcb 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -181,8 +181,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
 			RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
 
 			if (a.is_fully_const()) {
-				RTLIL::SigSpec tmp = a;
-				a = b, b = tmp;
+				RTLIL::SigSpec tmp;
+				tmp = a, a = b, b = tmp;
+				cell->connections["\\A"] = a;
+				cell->connections["\\B"] = b;
 			}
 
 			if (b.is_fully_const()) {