From: Cole Poirier <colepoirier@gmail.com>
Date: Mon, 10 Aug 2020 16:10:51 +0000 (-0700)
Subject: Fix bug 450 comment 7
X-Git-Tag: semi_working_ecp5~410
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c632ea3b5094f5c43b679504402e0b17d7799497;p=soc.git

Fix bug 450 comment 7
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index d5cba5a2..e4779962 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -572,7 +572,7 @@ class AddrShifter(Elaboratable):
 #           -- rts == radix tree size, # address bits being translated
 #           rts := unsigned('0' & pgtbl(62 downto 61) & pgtbl(7 downto 5));
             # rts == radix tree size, number of address bits being translated
-            comb += rts.eq((0 & pgtbl[61:63] & pgtbl[5:8]).as_unsigned())
+            comb += rts.eq(((Cat(Const(0b0, 1) , Cat(pgtbl[61:63], pgtbl[5:8]))).as_unsigned())
 
 #           -- mbits == # address bits to index top level of tree
 #           mbits := unsigned('0' & pgtbl(4 downto 0));