From: lkcl Date: Sat, 26 Dec 2020 17:09:46 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~842 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c634bab65e402a358f781a462e47feeeb709bd2b;p=libreriscv.git --- diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn new file mode 100644 index 000000000..2066caef9 --- /dev/null +++ b/openpower/sv/svp64/appendix.mdwn @@ -0,0 +1,491 @@ +# Appendix + +## XER, SO and other global flags + +Vector systems are expected to be high performance. This is achieved +through parallelism, which requires that elements in the vector be +independent. XER SO and other global "accumulation" flags (CR.OV) cause +Read-Write Hazards on single-bit global resources, having a significant +detrimental effect. + +Consequently in SV, XER.SO and CR.OV behaviour is disregarded (including in cmp ibstructions) . XER is +simply neither read nor written. This includes when `scalar identity behaviour` occurs. If precise OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1 instructions should be used without an SV Prefix. + +An interesting side-effect of this decision is that the OE flag is now free for other uses when SV Prefixing is used. + +Regarding XER.CA: this does not fit either: it was designed for a scalar ISA. Instead, both carry-in and carry-out go into the CR.so bit of a given Vector element. This provides a means to perform large parallel batches of Vectorised carry-capable additions. crweird instructions can be used to transfer the CRs in and out of an integer, where bitmanipulation may be performed to analyse the carry bits (including carry lookahead propagation) before continuing with further parallel additions. + +## v3.0B/v3.1B relevant instructions + +SV is primarily designed for use as an efficient hybrid 3D GPU / VPU / CPU ISA. + +As mentioned above, OE=1 is not applicable in SV, freeing this bit for alternative uses. Additionally, Vectorisation of the VSX SIMD system likewise makes no sense whatsoever. SV *replaces* VSX and provides, at the very minimum, predication (which VSX was designed without). Thus all VSX Major Opcodes - all of them - are "unused" and must raise illegal instruction exceptions in SV Prefix Mode. + +Likewise, `lq` (Load Quad), and Load/Store Multiple make no sense to have because they are not only provided by SV, the SV alternatives may be predicated as well, making them far better suited to use in function calls and context-switching. + +Additionally, some v3.0/1 instructions simply make no sense at all in a Vector context: `twi` and `tdi` fall into this category, as do branch operations as well as `sc` and `scv`. Here there is simply no point trying to Vectorise them: the standard OpenPOWER v3.0/1 instructions should be called instead. + +Fortuitously this leaves several Major Opcodes free for use by SV to fit alternative future instructions. In a 3D context this means Vector Product, Vector Normalise, [[sv/mv.swizzle]], Texture LD/ST operations, and others critical to an efficient, effective 3D GPU and VPU ISA. With such instructions being included as standard in other commercially-successful GPU ISAs it is likewise critical that a 3D GPU/VPU based on svp64 also have such instructions. + +Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions, and their discussion and specification is out of scope for this document. + +Note, again: this is *only* under svp64 prefixing. Standard v3.0B / v3.1B is *not* altered by svp64 in any way. + +### Major opcode map (v3.0B) + +This table is taken from v3.0B. +Table 9: Primary Opcode Map (opcode bits 0:5) + + | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 + 000 | | | tdi | twi | EXT04 | | | mulli | 000 + 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001 + 010 | bc/l/a | EXT17 | b/l/a | EXT19 | rlwimi| rlwinm | | rlwnm | 010 + 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011 + 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100 + 101 | lhz | lhzu | lha | lhau | sth | sthu | lmw | stmw | 101 + 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110 + 111 | lq | EXT57 | EXT58 | EXT59 | EXT60 | EXT61 | EXT62 | EXT63 | 111 + | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 + +### Suitable for svp64 + +This is the same table containing v3.0B Primary Opcodes except those that make mo sense in a Vectorisation Context have been removed. These removed POs can, *in the SV Vector Context only*, be assigned to alternative (Vectorised-only) instructions, including future extensions. + +Note, again, to emphasise: outside of svp64 these opcodes **do not** change. When not prefixed with svp64 these opcodes **specifically** retain their v3.0B / v3.1B OpenPOWER Standard compliant meaning. + + | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 + 000 | | | | | | | | mulli | 000 + 001 | subfic | | cmpli | cmpi | addic | addic. | addi | addis | 001 + 010 | | | | EXT19 | rlwimi| rlwinm | | rlwnm | 010 + 011 | ori | oris | xori | xoris | andi. | andis. | EXT30 | EXT31 | 011 + 100 | lwz | lwzu | lbz | lbzu | stw | stwu | stb | stbu | 100 + 101 | lhz | lhzu | lha | lhau | sth | sthu | | | 101 + 110 | lfs | lfsu | lfd | lfdu | stfs | stfsu | stfd | stfdu | 110 + 111 | | | EXT58 | EXT59 | | EXT61 | | EXT63 | 111 + | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 + +## Twin Predication + +This is a novel concept that allows predication to be applied to a single +source and a single dest register. The following types of traditional +Vector operations may be encoded with it, *without requiring explicit +opcodes to do so* + +* VSPLAT (a single scalar distributed across a vector) +* VEXTRACT (like LLVM IR [`extractelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#extractelement-instruction)) +* VINSERT (like LLVM IR [`insertelement`](https://releases.llvm.org/11.0.0/docs/LangRef.html#insertelement-instruction)) +* VCOMPRESS (like LLVM IR [`llvm.masked.compressstore.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-compressstore-intrinsics)) +* VEXPAND (like LLVM IR [`llvm.masked.expandload.*`](https://releases.llvm.org/11.0.0/docs/LangRef.html#llvm-masked-expandload-intrinsics)) + +Those patterns (and more) may be applied to: + +* mv (the usual way that V\* ISA operations are created) +* exts\* sign-extension +* rwlinm and other RS-RA shift operations (**note**: excluding + those that take RA as both a src and dest. These are not + 1-src 1-dest, they are 2-src, 1-dest) +* LD and ST (treating AGEN as one source) +* FP fclass, fsgn, fneg, fabs, fcvt, frecip, fsqrt etc. +* Condition Register ops mfcr, mtcr and other similar + +This is a huge list that creates extremely powerful combinations, +particularly given that one of the predicate options is `(1<>2) # top 3 bits but BE + bit_index = 3-(BA & 0b11) # low 2 bits but BE + CR_reg = CR[CR_index] # get the CR + # finally get the bit from the CR. + CR_bit = (CR_reg & (1<> 2)<<5) | # hi 3 bits shifted up + (spec[0:1]<<3) | # to make room for these + (BA & 0b11) # CR_bit on the end + else: + # scalar constructs "0 spec[0:1] BA[0:4]" + return (spec[0:1] << 5) | BA + +Thus, for example, to access a given bit for a CR in SV mode, the v3.0B +algorithm to determin CR\_reg is modified to as follows: + + CR_index = 7-(BA>>2) # top 3 bits but BE + if spec[2]: + # vector mode + CR_index = (CR_index<<3) | (spec[0:1] << 1) + else: + # scalar mode + CR_index = (spec[0:1]<<3) | CR_index + # same as for v3.0/v3.1 from this point onwards + bit_index = 3-(BA & 0b11) # low 2 bits but BE + CR_reg = CR[CR_index] # get the CR + # finally get the bit from the CR. + CR_bit = (CR_reg & (1< 0 + ... etc + +If a "cumulated" CR based analysis of results is desired (a la VSX CR6) +then a followup instruction must be performed, setting "reduce" mode on +the Vector of CRs, using cr ops (crand, crnor)to do so. This provides far +more flexibility in analysing vectors than standard Vector ISAs. Normal +Vector ISAs are typically restricted to "were all results nonzero" and +"were some results nonzero". The application of mapreduce to Vectorised +cr operations allows far more sophisticated analysis, particularly in +conjunction with the new crweird operations see [[sv/cr_int_predication]]. + +Note in particular that the use of a separate instruction in this way +ensures that high performance multi-issue OoO inplementations do not +have the computation of the cumulative analysis CR as a bottleneck and +hindrance, regardless of the length of VL. + +(see [[discussion]]. some alternative schemes are described there) + +### Rc=1 when SUBVL!=1 + +sub-vectors are effectively a form of SIMD (length 2 to 4). Only 1 bit of predicate is allocated per subvector; likewise only one CR is allocated +per subvector. + +This leaves a conundrum as to how to apply CR computation per subvector, when normally Rc=1 is exclusively applied to scalar elements. A solution is to perform a bitwise OR or AND of the subvector tests. Given that OE is ignored, rhis field may (when available) be used to select OR or AND behavior. + +### Table of CR fields + +CR[i] is the notation used by the OpenPower spec to refer to CR field #i, +so FP instructions with Rc=1 write to CR[1] aka SVCR1_000. + +CRs are not stored in SPRs: they are registers in their own right. +Therefore context-switching the full set of CRs involves a Vectorised +mfcr or mtcr, using VL=64, elwidth=8 to do so. This is exactly as how scalar OpenPOWER context-switches CRs: it is just that there are now more of them. + +The 64 SV CRs are arranged similarly to the way the 128 integer registers +are arranged. TODO a python program that auto-generates a CSV file +which can be included in a table, which is in a new page (so as not to +overwhelm this one). [[svp64/cr_names]] + +## Register Profiles + +**NOTE THIS TABLE SHOULD NO LONGER BE HAND EDITED** see + for details. + +Instructions are broken down by Register Profiles as listed in the +following auto-generated page: [[opcode_regs_deduped]]. "Non-SV" +indicates that the operations with this Register Profile cannot be +Vectorised (mtspr, bc, dcbz, twi) + +TODO generate table which will be here [[svp64/reg_profiles]] + +## SV pseudocode illilustration + +### Single-predicated Instruction + +illustration of normal mode add operation: zeroing not included, elwidth overrides not included. if there is no predicate, it is set to all 1s + + function op_add(rd, rs1, rs2) # add not VADD! + int i, id=0, irs1=0, irs2=0; + predval = get_pred_val(FALSE, rd); + for (i = 0; i < VL; i++) + STATE.srcoffs = i # save context + if (predval & 1< + +## Assembly Annotation + +Assembly code annotation is required for SV to be able to successfully +mark instructions as "prefixed". + +A reasonable (prototype) starting point: + + svp64 [field=value]* + +Fields: + +* ew=8/16/32 - element width +* sew=8/16/32 - source element width +* vec=2/3/4 - SUBVL +* mode=reduce/satu/sats/crpred +* pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne +* spred={reg spec} + +similar to x86 "rex" prefix.