From: Luke Kenneth Casson Leighton Date: Sun, 31 May 2020 11:33:30 +0000 (+0100) Subject: remove commented-out vars from ALU input record X-Git-Tag: div_pipeline~723 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6374650fdc2eac5111c8db7a04f0f9b60955c11;p=soc.git remove commented-out vars from ALU input record --- diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py index f95c16d3..472eaaf4 100644 --- a/src/soc/fu/alu/alu_input_record.py +++ b/src/soc/fu/alu/alu_input_record.py @@ -14,8 +14,6 @@ class CompALUOpSubset(Record): layout = (('insn_type', InternalOp), ('fn_unit', Function), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), - #'cr = Signal(32, reset_less=True) # NO: this is from the CR SPR - #'xerc = XerBits() # NO: this is from the XER SPR ('lk', 1), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data @@ -39,8 +37,6 @@ class CompALUOpSubset(Record): # grrr. Record does not have kwargs self.insn_type.reset_less = True self.fn_unit.reset_less = True - #self.cr = Signal(32, reset_less = True - #self.xerc = XerBits( self.lk.reset_less = True self.zero_a.reset_less = True self.invert_a.reset_less = True @@ -66,8 +62,6 @@ class CompALUOpSubset(Record): def ports(self): return [self.insn_type, - #self.cr, - #self.xerc, self.lk, self.invert_a, self.invert_out,