From: Owen W. Taylor <otaylor@fishsoup.net>
Date: Sat, 20 Nov 2010 17:18:56 +0000 (-0500)
Subject: r600g: Fix location for clip plane registers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c63a86e1e5665fb5cd94de42d6c59171398e12ee;p=mesa.git

r600g: Fix location for clip plane registers

The stride between the different clip plane registers was incorrect.

https://bugs.freedesktop.org/show_bug.cgi?id=31788

agd5f: fix evergreen as well.
---

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 8558e3b559a..26dad7b65c0 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -501,16 +501,16 @@ static void evergreen_set_clip_state(struct pipe_context *ctx,
 	rstate->id = R600_PIPE_STATE_CLIP;
 	for (int i = 0; i < state->nr; i++) {
 		r600_pipe_state_add_reg(rstate,
-					R_0285BC_PA_CL_UCP0_X + i * 4,
+					R_0285BC_PA_CL_UCP0_X + i * 16,
 					fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate,
-					R_0285C0_PA_CL_UCP0_Y + i * 4,
+					R_0285C0_PA_CL_UCP0_Y + i * 16,
 					fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate,
-					R_0285C4_PA_CL_UCP0_Z + i * 4,
+					R_0285C4_PA_CL_UCP0_Z + i * 16,
 					fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate,
-					R_0285C8_PA_CL_UCP0_W + i * 4,
+					R_0285C8_PA_CL_UCP0_W + i * 16,
 					fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
 	}
 	r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 6fd46ae7e69..bf4ca057d28 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -692,16 +692,16 @@ static void r600_set_clip_state(struct pipe_context *ctx,
 	rstate->id = R600_PIPE_STATE_CLIP;
 	for (int i = 0; i < state->nr; i++) {
 		r600_pipe_state_add_reg(rstate,
-					R_028E20_PA_CL_UCP0_X + i * 4,
+					R_028E20_PA_CL_UCP0_X + i * 16,
 					fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate,
-					R_028E24_PA_CL_UCP0_Y + i * 4,
+					R_028E24_PA_CL_UCP0_Y + i * 16,
 					fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate,
-					R_028E28_PA_CL_UCP0_Z + i * 4,
+					R_028E28_PA_CL_UCP0_Z + i * 16,
 					fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate,
-					R_028E2C_PA_CL_UCP0_W + i * 4,
+					R_028E2C_PA_CL_UCP0_W + i * 16,
 					fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
 	}
 	r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,