From: Florent Kermarrec Date: Fri, 7 Jun 2019 09:14:36 +0000 (+0200) Subject: soc/integration/soc_core: list rocket as supported CPU X-Git-Tag: 24jan2021_ls180~1180 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c64129dc69fb4db42a2c5df5386e65c1fd5b51ed;p=litex.git soc/integration/soc_core: list rocket as supported CPU --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 7d48f248..4e03b531 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -576,7 +576,7 @@ class SoCCore(Module): def soc_core_args(parser): parser.add_argument("--cpu-type", default=None, - help="select CPU: lm32, or1k, picorv32, vexriscv, minerva") + help="select CPU: lm32, or1k, picorv32, vexriscv, minerva, rocket") parser.add_argument("--cpu-variant", default=None, help="select CPU variant") parser.add_argument("--integrated-rom-size", default=None, type=int,