From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 28 May 2023 22:04:55 +0000 (+0300)
Subject: ppc/svp64: support bmask instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c65cd0054d8e24571aba36bb5794fcfb3436c378;p=binutils-gdb.git

ppc/svp64: support bmask instruction
---

diff --git a/gas/testsuite/gas/ppc/bmask.d b/gas/testsuite/gas/ppc/bmask.d
new file mode 100644
index 00000000000..1daf05e49c7
--- /dev/null
+++ b/gas/testsuite/gas/ppc/bmask.d
@@ -0,0 +1,13 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(5b e0 00 11|11 00 e0 5b)\s+bmask\s+r31,r0,r0,0,0
+.*:\s+(58 1f 00 11|11 00 1f 58)\s+bmask\s+r0,r31,r0,0,0
+.*:\s+(58 00 f8 11|11 f8 00 58)\s+bmask\s+r0,r0,r31,0,0
+.*:\s+(58 00 07 d1|d1 07 00 58)\s+bmask\s+r0,r0,r0,31,0
+.*:\s+(58 00 00 31|31 00 00 58)\s+bmask\s+r0,r0,r0,0,1
diff --git a/gas/testsuite/gas/ppc/bmask.s b/gas/testsuite/gas/ppc/bmask.s
new file mode 100644
index 00000000000..95ff8a0ba58
--- /dev/null
+++ b/gas/testsuite/gas/ppc/bmask.s
@@ -0,0 +1,5 @@
+bmask 31,0,0,0,0
+bmask 0,31,0,0,0
+bmask 0,0,31,0,0
+bmask 0,0,0,31,0
+bmask 0,0,0,0,1
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 3cf89e13bfc..7eb87fa93b5 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -166,3 +166,4 @@ run_dump_test "fishmv"
 run_dump_test "avgadd"
 run_dump_test "cprop"
 run_dump_test "absd"
+run_dump_test "bmask"
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 91adabb9517..12491688e34 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3037,6 +3037,8 @@ const struct powerpc_operand powerpc_operands[] =
 #define MB CRB
 #define MB_MASK (0x1f << 6)
   { 0x1f, 6, NULL, NULL, 0 },
+  /* The bm field in an BM2 form instruction.  */
+#define bm CRB
 
   /* The CRD32 field in an XL form instruction.  */
 #define CRD32 CRB + 1
@@ -4028,6 +4030,9 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define SVo mi2 + 1
   { 0xf, 22, NULL, NULL, 0 },
+
+#define LBM2 SVo + 1
+  { 0x1, 5, NULL, NULL, 0 },
 };
 
 const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
@@ -4945,6 +4950,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
    | (((uint64_t)(xop)) & 0x3f))
 #define SVI_MASK	SVI (0x3f, 0x3f)
 
+/* An BM2 form instruction. */
+#define BM2(op, xop)				\
+  (OP (op)					\
+   | (((uint64_t)(xop)) & 0x1f))
+#define BM2_MASK	BM2 (0x3f, 0x1f)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF	(0x0)
 #define BODNZFP	(0x1)
@@ -7019,6 +7030,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fmvis",	DX(22,3),	DX_MASK,	SVP64,	PPCVLE,	{FRS, DXD}},
 {"fishmv",	DX(22,11),	DX_MASK,	SVP64,	PPCVLE,	{FRS, DXD}},
 
+{"bmask",	BM2(22,17),	BM2_MASK,	SVP64,	PPCVLE,	{RT, RA, RB, bm, LBM2}},
+
 {"svstep",	SVL(22,19,0),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},
 {"svstep.",	SVL(22,19,1),	SVL_MASK,	SVP64,	PPCVLE,	{RT, SVi, vf}},