From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 18 Sep 2019 19:44:34 +0000 (-0700)
Subject: Remove stat
X-Git-Tag: working-ls180~1039^2~98
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c663a3680b13422c568e3dc438e7b971b81a71c3;p=yosys.git

Remove stat
---

diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
index 30c034afe..77990bd68 100644
--- a/tests/xilinx/mul_unsigned.ys
+++ b/tests/xilinx/mul_unsigned.ys
@@ -4,7 +4,6 @@ hierarchy -top mul_unsigned
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module
-stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:DSP48E1
 select -assert-count 30 t:FDRE