From: lkcl <lkcl@web>
Date: Fri, 8 Jan 2021 05:20:59 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~562
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c673b8c5109722fce9d760d6db91553b8bddc33f;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 4ff5882e1..d34ca4868 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -38,12 +38,14 @@ a 4 operand variant which becomes more along the lines of an FPGA:
 
 | 0.5|6.10|11.15|16.20| 21..22 | 23...30 |31|  name   |
 | -- | -- | --- | --- | ------ | ------- |--| ------- |
-| NN | RT | RA  | RB  | 1   0  | RC ///  |Rc| XL-Form |
+| NN | RT | RA  | RB  | 1   0  | RC mode |Rc| XL-Form |
 
     for i in range(64):
         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
         RT[i] = (RC & (1<<idx)) != 0
 
+mode may be used to do inversion of ordering, similar to carryless mul
+
 another mode selection would be CRs not Ints. 
 
 | 0.5|6.8 | 9.11|12.14|15.17|18.21|22 | 23...30 |31|  name   |
@@ -208,7 +210,7 @@ return x;
 
 # cmix
 
-based on RV bitmanip
+based on RV bitmanip, covered by ternary bitops
 
 ```
 uint_xlen_t cmix(uint_xlen_t rs1, uint_xlen_t rs2, uint_xlen_t rs3) {