From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Sun, 24 May 2020 14:37:24 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6a286c95889bc55f5db085d9555e19968738124;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
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diff --git a/35/e947945b8b8458ae8af0ec33d3c1803766f717 b/35/e947945b8b8458ae8af0ec33d3c1803766f717
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+Date: Sun, 24 May 2020 14:37:24 +0000
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-5fN1SARAfy@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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