From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Tue, 19 Apr 2011 05:55:28 +0000 (-0700)
Subject: [xcc,sim] rv64 'w' instruction semantics changed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c6b549289aa0f6d975307ebdddbbd6b8b0a31e7e;p=riscv-isa-sim.git

[xcc,sim] rv64 'w' instruction semantics changed

they no longer require their inputs to be canonicalized 32b values, so
this speeds up mixed int/long code sequences.
---

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index 18fc55b..bb17d27 100644
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -4,5 +4,5 @@ else
 {
   if(SHAMT & 0x20)
     throw trap_illegal_instruction;
-  RD = sext32(sreg_t(RS1) >> SHAMT);
+  RD = sext32(int32_t(RS1) >> SHAMT);
 }
diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 42d0fc3..4c56730 100644
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(sreg_t(RS1) >> SHAMTW);
+RD = sext32(int32_t(RS1) >> SHAMTW);